Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor （CMP） design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this...Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor （CMP） design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies. Components of our BACH design include a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory （STT-MRAM）, resistive memory （ReRAM）, and embedded DRAM （eDRAM）, to configure each level so that the peak bandwidth of the overall cache hierarchy is optimized. Our reconfiguration mechanism can dynamically adjust the cache capacity of each level based on the predicted bandwidth demands of running workloads. The bandwidth prediction is performed by our prediction engine. We evaluate the system performance gain obtained by BACH design with a set of multithreaded and multiprogrammed workloads with and without the limitation of system power budget. Compared with traditional SRAM-based cache design, BACH improves the system throughput by 58% and 14% with multithreaded and multiprogrammed workloads respectively.展开更多
It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computi...It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computing abil- ity and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more effi- ciently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we pro- pose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format. With the block- ing method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU mem- ory bandwidth and the performance of the GPU.展开更多
提出一种支持动态搜索区域的可变块大小运动估计硬件结构,弥补固定大小搜索区域的不足,可同时降低外存带宽、计算复杂度和功耗.使用循环分布式存储结构来支持动态搜索区域的数据存取.此外,对耗时的SAD(sum of absolute differences)计...提出一种支持动态搜索区域的可变块大小运动估计硬件结构,弥补固定大小搜索区域的不足,可同时降低外存带宽、计算复杂度和功耗.使用循环分布式存储结构来支持动态搜索区域的数据存取.此外,对耗时的SAD(sum of absolute differences)计算阵列进行均衡的流水线划分和加法逻辑优化.实现结果表明,相比同类设计,该设计以少量的吞吐率损失,换取面积效率和功耗效率的明显提高.展开更多
文摘Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor （CMP） design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies. Components of our BACH design include a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory （STT-MRAM）, resistive memory （ReRAM）, and embedded DRAM （eDRAM）, to configure each level so that the peak bandwidth of the overall cache hierarchy is optimized. Our reconfiguration mechanism can dynamically adjust the cache capacity of each level based on the predicted bandwidth demands of running workloads. The bandwidth prediction is performed by our prediction engine. We evaluate the system performance gain obtained by BACH design with a set of multithreaded and multiprogrammed workloads with and without the limitation of system power budget. Compared with traditional SRAM-based cache design, BACH improves the system throughput by 58% and 14% with multithreaded and multiprogrammed workloads respectively.
文摘It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computing abil- ity and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more effi- ciently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we pro- pose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format. With the block- ing method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU mem- ory bandwidth and the performance of the GPU.
文摘提出一种支持动态搜索区域的可变块大小运动估计硬件结构,弥补固定大小搜索区域的不足,可同时降低外存带宽、计算复杂度和功耗.使用循环分布式存储结构来支持动态搜索区域的数据存取.此外,对耗时的SAD(sum of absolute differences)计算阵列进行均衡的流水线划分和加法逻辑优化.实现结果表明,相比同类设计,该设计以少量的吞吐率损失,换取面积效率和功耗效率的明显提高.
