Engineering application domains need database management systems to supply them with a good means of modeling, a high data access efficiency and a language interface with strong functionality. This paper presents a se...Engineering application domains need database management systems to supply them with a good means of modeling, a high data access efficiency and a language interface with strong functionality. This paper presents a semantic hypergraph model based on relations, in order to express many-to-many relations among objects belonging to defferent semanic classes in engineering applications. A management mechanism expressed by the model and the basic data of engineering databases are managed in main memory. Especially, different objects are linked by different kinds of semantics defined by users, therefore the table swap, the record swap and some unnecessary examinations are reduced and the access efficiency of the engineering data is increased.C language interface that includes some generic and special functionality is proposed for closer connection with application programs.展开更多
Electric-induced resistive switching effects have attracted wide attention for future nonvolatile memory applications known as resistive random access memory(RRAM).RRAM is one of the promising candidates because of it...Electric-induced resistive switching effects have attracted wide attention for future nonvolatile memory applications known as resistive random access memory(RRAM).RRAM is one of the promising candidates because of its excellent properties including simple device structure,high operation speed,low power consumption and high density integration.The RRAM devices pri-marily utilize different resistance values to store the digital data and can keep the resistance state without any power.Recent advances in the understanding of the resistive switching mechanism are described by a thermal or electrochemical redox reaction near the interface between the oxide and the active metal electrode.This paper reviews the ongoing research and development activities on the interface engineering of the RRAM devices.The possible switching mechanisms for the bistable resistive switching are described.The effects of formation,composition and thickness of the interface layer on the resistive switching characteristics and consequently the memory performance are also discussed.展开更多
An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline ...An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with traditional debug mode,the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access(DT-DMA)module,which improves debug efficiency greatly.The proposed circuit was designed in a 0.18μm complementary metal-oxide-semiconductor(CMOS)process with an area of 167234.76μm~2 and a power consumption of 8.89 mW.And the proposed debug circuit and L-DSP were verified under a field programmable gate array(FPGA).Experimental results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.展开更多
红外目标识别系统中 ,需要实时采集红外传感器的图像数据。本文描述了一种基于 CPCI总线的红外图像数据采集卡。此卡采用 CPCI总线控制器中 F IF O通道的 DMA方式进行高速图像数据传输 ,保证了数据传输的实时性和准确性 ,满足了系统对...红外目标识别系统中 ,需要实时采集红外传感器的图像数据。本文描述了一种基于 CPCI总线的红外图像数据采集卡。此卡采用 CPCI总线控制器中 F IF O通道的 DMA方式进行高速图像数据传输 ,保证了数据传输的实时性和准确性 ,满足了系统对大数据量的存储要求。此采集电路对于多种红外传感器具有良好的兼容性 ,在实地采集数据中得到了良好的原始红外图像数据。展开更多
文摘Engineering application domains need database management systems to supply them with a good means of modeling, a high data access efficiency and a language interface with strong functionality. This paper presents a semantic hypergraph model based on relations, in order to express many-to-many relations among objects belonging to defferent semanic classes in engineering applications. A management mechanism expressed by the model and the basic data of engineering databases are managed in main memory. Especially, different objects are linked by different kinds of semantics defined by users, therefore the table swap, the record swap and some unnecessary examinations are reduced and the access efficiency of the engineering data is increased.C language interface that includes some generic and special functionality is proposed for closer connection with application programs.
文摘Electric-induced resistive switching effects have attracted wide attention for future nonvolatile memory applications known as resistive random access memory(RRAM).RRAM is one of the promising candidates because of its excellent properties including simple device structure,high operation speed,low power consumption and high density integration.The RRAM devices pri-marily utilize different resistance values to store the digital data and can keep the resistance state without any power.Recent advances in the understanding of the resistive switching mechanism are described by a thermal or electrochemical redox reaction near the interface between the oxide and the active metal electrode.This paper reviews the ongoing research and development activities on the interface engineering of the RRAM devices.The possible switching mechanisms for the bistable resistive switching are described.The effects of formation,composition and thickness of the interface layer on the resistive switching characteristics and consequently the memory performance are also discussed.
基金supported by the China-Montenegro 3rd Science&Technology Exchange and Cooperation Project(3-7)the Open Research Fund of Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering(202005)the Double First-Class Scientific Research International Cooperation Expansion Project of Changsha University of Science&Technology(2019ic18)。
文摘An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with traditional debug mode,the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access(DT-DMA)module,which improves debug efficiency greatly.The proposed circuit was designed in a 0.18μm complementary metal-oxide-semiconductor(CMOS)process with an area of 167234.76μm~2 and a power consumption of 8.89 mW.And the proposed debug circuit and L-DSP were verified under a field programmable gate array(FPGA).Experimental results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.
