This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise...This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.展开更多
A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral transformer as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measur...A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral transformer as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measured phase noise is -125.7 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.6 GHz while the VCO core circuit draws only of 10 mW from a 1.8 V supply. The measured phase error is approximately 1.5° based on the time domain outputs and the output power is about -2 dBm. The VCO can cover the frequency range of 4.36-4.68 GHz. The tuning range is 320 MHz （7.0%） and the FOM is -189 dB.展开更多
A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In ...A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than -107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35 %. The results led to a good oscillator figure of merit of-188 dBc/Hz. The measurement results agreed well with those of the simulations.展开更多
将DDS技术应用于超短波射频通信频率源中,比较了几种常见的小步进频率源的设计方案,设计实现了一种＂锁相环-直接数字频率合成器-锁相环＂（PLL＋DDS＋PLL）结构的高性能频率源。与传统的频率源设计相比,新的设计更能够满足工程应用过...将DDS技术应用于超短波射频通信频率源中,比较了几种常见的小步进频率源的设计方案,设计实现了一种＂锁相环-直接数字频率合成器-锁相环＂（PLL＋DDS＋PLL）结构的高性能频率源。与传统的频率源设计相比,新的设计更能够满足工程应用过程中小步进、低相噪、高集成度的需求;设计频率源输出频率范围为1 766.5~1 771.5 MHz,步进0.000 5 Hz,相位噪声在距输出频率10 k Hz处小于–95 d Bc,杂散抑制度优于70 d Bc。展开更多
基金Project supported by the Project on the Integration of Industry,Education and Research of Guangdong Province,China(No.2012B090600035)
文摘This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.
基金supported by the National Natural Science Foundation of China (No. 60772008).
文摘A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral transformer as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measured phase noise is -125.7 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.6 GHz while the VCO core circuit draws only of 10 mW from a 1.8 V supply. The measured phase error is approximately 1.5° based on the time domain outputs and the output power is about -2 dBm. The VCO can cover the frequency range of 4.36-4.68 GHz. The tuning range is 320 MHz （7.0%） and the FOM is -189 dB.
文摘A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than -107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35 %. The results led to a good oscillator figure of merit of-188 dBc/Hz. The measurement results agreed well with those of the simulations.
文摘将DDS技术应用于超短波射频通信频率源中,比较了几种常见的小步进频率源的设计方案,设计实现了一种＂锁相环-直接数字频率合成器-锁相环＂（PLL＋DDS＋PLL）结构的高性能频率源。与传统的频率源设计相比,新的设计更能够满足工程应用过程中小步进、低相噪、高集成度的需求;设计频率源输出频率范围为1 766.5~1 771.5 MHz,步进0.000 5 Hz,相位噪声在距输出频率10 k Hz处小于–95 d Bc,杂散抑制度优于70 d Bc。
