A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including ...A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.展开更多
A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range o...A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage. Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges. Realized in 0.25μm CMOS technology, a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from - 17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.展开更多
A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based techniqu...A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.展开更多
A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The...A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.展开更多
A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linea...A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.展开更多
In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technol...In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.展开更多
文摘A high-linearity PGA（programmable gain amplifier） with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA（RXPGA） provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA（TXPGA） covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA （I and Q path） under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC（DC offset cancellation） circuit shows 10 kHz of HPCF（high pass cutoff frequency） and the DCOC settling time is less than 0.45μs.
文摘A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage. Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges. Realized in 0.25μm CMOS technology, a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from - 17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.
文摘A low-power high-linearity linear-in-dB variable gain amplifier（VGA） with novel DC offset calibration loop for direct-conversion receiver（DCR） is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier（PGA） can be converted to an analog controlled dB-linear VGA. An operational amplifier（OPAMP） utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation（DCOC） loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm^2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency（HPCF） and the measured residual DC offset at the output of VGA is less than 2 mV.
文摘A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.
文摘A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.
文摘In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.
