In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed....In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.展开更多
A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cy...A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid ＂false locking＂. Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18μm CMOS technology, and its core area occupies 0.7 x 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 4-0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.展开更多
A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a...A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.展开更多
基金Supported by the National Basic Research Program of China(No.2010CB327404)
文摘In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.
基金supported by the National Science and Technology Major Project(No.2011ZX03004-002-01)the Fundamental Research Funds for the Central Universities(No.WK2100230012)
文摘A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid ＂false locking＂. Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18μm CMOS technology, and its core area occupies 0.7 x 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 4-0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.
文摘A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.
