The generation of electricity based on renewable energy sources,parti-cularly Photovoltaic(PV)system has been greatly increased and it is simply insti-gated for both domestic and commercial uses.The power generated fr...The generation of electricity based on renewable energy sources,parti-cularly Photovoltaic(PV)system has been greatly increased and it is simply insti-gated for both domestic and commercial uses.The power generated from the PV system is erratic and hence there is a need for an efficient converter to perform the extraction of maximum power.An improved interleaved Single-ended Primary Inductor-Converter(SEPIC)converter is employed in proposed work to extricate most of power from renewable source.This proposed converter minimizes ripples,reduces electromagnetic interference due tofilter elements and the contin-uous input current improves the power output of PV panel.A Crow Search Algo-rithm(CSA)based Proportional Integral(PI)controller is utilized for controlling the converter switches effectively by optimizing the parameters of PI controller.The optimized PI controller reduces ripples present in Direct Current(DC)vol-tage,maintains constant voltage at proposed converter output and reduces over-shoots with minimum settling and rise time.This voltage is given to single phase grid via 1�Voltage Source Inverter(VSI).The command pulses of 1�VSI are produced by simple PI controller.The response of the proposed converter is thus improved with less input current.After implementing CSA based PI the efficiency of proposed converter obtained is 96%and the Total Harmonic Distor-tion(THD)is found to be 2:4%.The dynamics and closed loop operation is designed and modeled using MATLAB Simulink tool and its behavior is performed.展开更多
The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BI...The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.展开更多
A new method to construct shift sequence sets is presented. Different shift sequence sets are obtained by changing parameters of the shift sequence. Based on these shift sequence sets, multiple shift distinct array se...A new method to construct shift sequence sets is presented. Different shift sequence sets are obtained by changing parameters of the shift sequence. Based on these shift sequence sets, multiple shift distinct array sets with zero-correlation zone （ZCZ） can be obtained by utilizing interleaving technique. It is shown that the resultant ZCZ array sets are optimal or almost optimal with respect to the Tang, Fan, and Matsufuji bound. Compared with previous methods, the proposed method extends the number of shift distinct ZCZ array sets.展开更多
A real-time dwell scheduling model, which takes the time and energy constraints into account is founded from the viewpoint of scheduling gain. Scheduling design is turned into a nonlinear programming procedure. The re...A real-time dwell scheduling model, which takes the time and energy constraints into account is founded from the viewpoint of scheduling gain. Scheduling design is turned into a nonlinear programming procedure. The real-time dwell scheduling algorithm based on the scheduling gain is presented with the help of two heuristic rules. The simulation results demonstrate that compared with the conventional adaptive scheduling method, the algorithm proposed not only increases the scheduling gain and the time utility but also decreases the task drop rate.展开更多
In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural o...In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput （40-100 Mbps）, the hardware cost is still affordable for 3GPP＇s （3rd generation partnership project） interleaver.展开更多
Aiming at the problem of resource allocation for digital array radar（ DAR）,a dwell scheduling algorithm is proposed in this paper. Firstly,the integrated priority of different radar tasks is designed,which ensures t...Aiming at the problem of resource allocation for digital array radar（ DAR）,a dwell scheduling algorithm is proposed in this paper. Firstly,the integrated priority of different radar tasks is designed,which ensures that the imaging tasks are scheduled without affecting the search and tracking tasks; Then,the optimal scheduling model of radar resource is established according to the constraints of pulse interleaving; Finally,a heuristic algorithm is used to solve the problem and a sparse-aperture cognitive ISAR imaging method is used to achieve partial precision tracking target imaging. Simulation results demonstrate that the proposed algorithm can both improve the performance of the radar system,and generate satisfactory imaging results.展开更多
文摘The generation of electricity based on renewable energy sources,parti-cularly Photovoltaic(PV)system has been greatly increased and it is simply insti-gated for both domestic and commercial uses.The power generated from the PV system is erratic and hence there is a need for an efficient converter to perform the extraction of maximum power.An improved interleaved Single-ended Primary Inductor-Converter(SEPIC)converter is employed in proposed work to extricate most of power from renewable source.This proposed converter minimizes ripples,reduces electromagnetic interference due tofilter elements and the contin-uous input current improves the power output of PV panel.A Crow Search Algo-rithm(CSA)based Proportional Integral(PI)controller is utilized for controlling the converter switches effectively by optimizing the parameters of PI controller.The optimized PI controller reduces ripples present in Direct Current(DC)vol-tage,maintains constant voltage at proposed converter output and reduces over-shoots with minimum settling and rise time.This voltage is given to single phase grid via 1�Voltage Source Inverter(VSI).The command pulses of 1�VSI are produced by simple PI controller.The response of the proposed converter is thus improved with less input current.After implementing CSA based PI the efficiency of proposed converter obtained is 96%and the Total Harmonic Distor-tion(THD)is found to be 2:4%.The dynamics and closed loop operation is designed and modeled using MATLAB Simulink tool and its behavior is performed.
文摘The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.
基金supported by the National Natural Science Foundation of China (61172094)the Natural Science Foundation of Hebei Province (F2012203171)
文摘A new method to construct shift sequence sets is presented. Different shift sequence sets are obtained by changing parameters of the shift sequence. Based on these shift sequence sets, multiple shift distinct array sets with zero-correlation zone （ZCZ） can be obtained by utilizing interleaving technique. It is shown that the resultant ZCZ array sets are optimal or almost optimal with respect to the Tang, Fan, and Matsufuji bound. Compared with previous methods, the proposed method extends the number of shift distinct ZCZ array sets.
文摘A real-time dwell scheduling model, which takes the time and energy constraints into account is founded from the viewpoint of scheduling gain. Scheduling design is turned into a nonlinear programming procedure. The real-time dwell scheduling algorithm based on the scheduling gain is presented with the help of two heuristic rules. The simulation results demonstrate that compared with the conventional adaptive scheduling method, the algorithm proposed not only increases the scheduling gain and the time utility but also decreases the task drop rate.
基金supported by the National High-Technology Research and Development Program of China （Grant No.2003AA123310）, and the National Natural Science Foundation of China （Grant Nos.60332030, 60572157）
文摘In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput （40-100 Mbps）, the hardware cost is still affordable for 3GPP＇s （3rd generation partnership project） interleaver.
基金Supported by the National Natural Science Foundation of China(61471386)
文摘Aiming at the problem of resource allocation for digital array radar（ DAR）,a dwell scheduling algorithm is proposed in this paper. Firstly,the integrated priority of different radar tasks is designed,which ensures that the imaging tasks are scheduled without affecting the search and tracking tasks; Then,the optimal scheduling model of radar resource is established according to the constraints of pulse interleaving; Finally,a heuristic algorithm is used to solve the problem and a sparse-aperture cognitive ISAR imaging method is used to achieve partial precision tracking target imaging. Simulation results demonstrate that the proposed algorithm can both improve the performance of the radar system,and generate satisfactory imaging results.
