As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient techniq...As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.展开更多
The silicon microring resonator plays an important role in large-scale,high-integrability modern switching matrixes and optical networks,as silicon photonics enables ring resonators of an unprecedented compact size.Bu...The silicon microring resonator plays an important role in large-scale,high-integrability modern switching matrixes and optical networks,as silicon photonics enables ring resonators of an unprecedented compact size.But as the nature of resonators is their sensitivity to temperature,their performances are vulnerable to being affected by thermal effect.In this paper,we analyze the dominant thermal effects to the application of silicon microring optical switch.On the one hand we theoretically analyze and experimentally measure the thermal crosstalk among adjacent microring optical switches with different distances,and give possible solutions to minimize the affect of thermal crosstalk.On the other hand we analyze and measure the thermooptic dynamic response of microring switch;the experiment shows for the thermal-tuning that the rising edge is around 2/is,and the falling edge is around 35 μs.We give the explanation of the asymmetric rise-time and fall-time.展开更多
The signal integrity problem in 0.18μm CMOS technology is analyzed from simulation.Several rules in this phenomenon are found by analyzing the crosstalk delay and noise,which are helpful for the future circuit design.
Crosstalk noise is one of the emerging issues in deep sub-micrometer technology which causes many undesired effects on the circuit performance. In this paper, a Crosstalk-Aware Routing Resource Assignment (CARRA) algo...Crosstalk noise is one of the emerging issues in deep sub-micrometer technology which causes many undesired effects on the circuit performance. In this paper, a Crosstalk-Aware Routing Resource Assignment (CARRA) algorithm is proposed, which integrates the routing layers and tracks to address the crosstalk noise issue during the track/layer assignment stage. The CARRA problem is formulated as a weighted bipartite matching problem and solved using the linear assignment algorithm. The crosstalk risks between nets are represented by an undirected graph and the maximum number of the concurrent crosstalk risking nets is computed as the max clique of the graph. Then the nets in each max clique are assigned to disadjacent tracks. Thus the crosstalk noise can be avoided based on the clique concept. The algorithm is tested on IBM benchmarks and the experimental results show that it can improve the final routing layout a lot with little loss of the completion rate.展开更多
Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources...Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .展开更多
Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects. Applying function approximati...Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects. Applying function approximation and model order-reduction to the model, we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition. For various interconnect coupling sizes, the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process. This model can be used in computer-aided-design of nanometer SOCs.展开更多
文摘As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient technique to reduce the inductive noise.In this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced first.Then base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed respectively.The results of experiments show that these two models both have high fidelity.
基金supported by the Natural National Science Foundation of China(Nos.61235001,61575187,61535002)
文摘The silicon microring resonator plays an important role in large-scale,high-integrability modern switching matrixes and optical networks,as silicon photonics enables ring resonators of an unprecedented compact size.But as the nature of resonators is their sensitivity to temperature,their performances are vulnerable to being affected by thermal effect.In this paper,we analyze the dominant thermal effects to the application of silicon microring optical switch.On the one hand we theoretically analyze and experimentally measure the thermal crosstalk among adjacent microring optical switches with different distances,and give possible solutions to minimize the affect of thermal crosstalk.On the other hand we analyze and measure the thermooptic dynamic response of microring switch;the experiment shows for the thermal-tuning that the rising edge is around 2/is,and the falling edge is around 35 μs.We give the explanation of the asymmetric rise-time and fall-time.
文摘The signal integrity problem in 0.18μm CMOS technology is analyzed from simulation.Several rules in this phenomenon are found by analyzing the crosstalk delay and noise,which are helpful for the future circuit design.
文摘Crosstalk noise is one of the emerging issues in deep sub-micrometer technology which causes many undesired effects on the circuit performance. In this paper, a Crosstalk-Aware Routing Resource Assignment (CARRA) algorithm is proposed, which integrates the routing layers and tracks to address the crosstalk noise issue during the track/layer assignment stage. The CARRA problem is formulated as a weighted bipartite matching problem and solved using the linear assignment algorithm. The crosstalk risks between nets are represented by an undirected graph and the maximum number of the concurrent crosstalk risking nets is computed as the max clique of the graph. Then the nets in each max clique are assigned to disadjacent tracks. Thus the crosstalk noise can be avoided based on the clique concept. The algorithm is tested on IBM benchmarks and the experimental results show that it can improve the final routing layout a lot with little loss of the completion rate.
基金This work was supported in part by the National Natural Science Foundation of China (Grant Nos. 69973027 and 60025101)by the National Fundamental Basic Research Program (973) (Grant No. G1999032903).
文摘Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .
文摘Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects. Applying function approximation and model order-reduction to the model, we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition. For various interconnect coupling sizes, the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process. This model can be used in computer-aided-design of nanometer SOCs.
