通过分析数字上变频器系统的工作过程及其主要参数对输出信噪比的影响,合理设计差分电压、预加重电路和高速串行发送器等的布局,有效提高数字上变频电路的性能.实际仿真和硬件测试表明,所设计的数字上变频器可将基带信号直接上变频到907...通过分析数字上变频器系统的工作过程及其主要参数对输出信噪比的影响,合理设计差分电压、预加重电路和高速串行发送器等的布局,有效提高数字上变频电路的性能.实际仿真和硬件测试表明,所设计的数字上变频器可将基带信号直接上变频到907.2 MHz频率上,实现阻带衰减达35 d B,提高了发射端信号的有效性和准确性,可以满足全数字发射机的应用要求.展开更多
A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM ...A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm^2.展开更多
文摘通过分析数字上变频器系统的工作过程及其主要参数对输出信噪比的影响,合理设计差分电压、预加重电路和高速串行发送器等的布局,有效提高数字上变频电路的性能.实际仿真和硬件测试表明,所设计的数字上变频器可将基带信号直接上变频到907.2 MHz频率上,实现阻带衰减达35 d B,提高了发射端信号的有效性和准确性,可以满足全数字发射机的应用要求.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010403)the National Natural Science Foundation of China(No.60801045)
文摘A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm^2.
文摘提出了一种应用于高速串行链路中的基于二阶预加重和阻抗校正技术的6 Gbit/s低功耗低抖动电压模(VM)发送器。在综合分析阻抗、供电电流和输出驱动器预加重等因素影响的基础上,采用了多种技术来提高发送器的信号完整性,主要包括:设计了一种阻抗校正电路(ICU)以保证50Ω的输出阻抗并抑制信号反射,提出了一种自偏置稳压器用来稳定电源电压,同时设计了一种信号边沿驱动器用以加速信号的转换时间。最终,整个发送器在65 nm CMOS工艺平台进行设计。后仿真结果表明,发送器工作在6 Gbit/s时,远端输出眼图高度大于800 m V,均方根抖动小于2.70 ps。发送器的功耗为16.1 m A,占用面积仅为370μm×230μm。
