In video applications, real-time image scaling techniques are often required. In this paper, an efficient implementation of a scaling engine based on 4×4 cubic convolution is proposed. The cubic convolution has a...In video applications, real-time image scaling techniques are often required. In this paper, an efficient implementation of a scaling engine based on 4×4 cubic convolution is proposed. The cubic convolution has a better performance than other traditional interpolation kernels and can also be realized on hardware. The engine is designed to perform arbitrary scaling ratios with an image resolution smaller than 2560× 1920 pixels and can scale up or down, in horizontal or vertical direction. It is composed of four fimctional units and five line buffers, which makes it more competitive than conventional architectures. A strict fixed-point strategy is applied to minimize the quantization errors of hardware realization. Experimental results show that the engine provides a better image quality and a comparatively lower hardware cost than reference implementations.展开更多
A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs o...A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.展开更多
基金supported by the National High-Tech R&D Program(863)of China(No.2009AA011706)the Fundamental Research Funds for the Central Universities(No.KYJD09012)
文摘In video applications, real-time image scaling techniques are often required. In this paper, an efficient implementation of a scaling engine based on 4×4 cubic convolution is proposed. The cubic convolution has a better performance than other traditional interpolation kernels and can also be realized on hardware. The engine is designed to perform arbitrary scaling ratios with an image resolution smaller than 2560× 1920 pixels and can scale up or down, in horizontal or vertical direction. It is composed of four fimctional units and five line buffers, which makes it more competitive than conventional architectures. A strict fixed-point strategy is applied to minimize the quantization errors of hardware realization. Experimental results show that the engine provides a better image quality and a comparatively lower hardware cost than reference implementations.
文摘A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.
