A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard f...A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.展开更多
This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS str...This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.展开更多
A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in ...A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.展开更多
基金Project supported by the National Natural Science Foundation of China(No.60976023)the National Science and Technology Major Project of China(Nos.2009ZX03007-001,2012ZX03004007-002)
文摘A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.
基金Project Supported by the National Science Fund for Creative Research Groups of China(No.60821062)the National Basic Research Program of China(No.2009CB320202)
文摘This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)the Special Fund of Jiangsu Province for the Transformation of Scientific and Technological Achievements(No.BA2010073)
文摘A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.
