针对基于光纤无线技术RoF的分布式天线系统架构,设计和实现了一种基于JEDEC的JESD207标准的射频-基带数字并行接口和Xi l i nx的高速串行Rocket IOTM技术、适用于分布式基站系统的射频-基带高速串行接口方案。该方案具有使用灵活、便于...针对基于光纤无线技术RoF的分布式天线系统架构,设计和实现了一种基于JEDEC的JESD207标准的射频-基带数字并行接口和Xi l i nx的高速串行Rocket IOTM技术、适用于分布式基站系统的射频-基带高速串行接口方案。该方案具有使用灵活、便于功能扩展和易于实现等特点,已用于基于RoF的无线通信实验系统。展开更多
针对串行通信过程中常用的CRC校验,在Xilinx ISE 10.1中采用IP核建立RAM,用以存入16 bit CRC校验余式表中的CRC校验码,采用VHDL语言完成了16 bit CRC校验查表法的设计。基于Xilinx公司ChipScope Pro Analyzer虚拟逻辑分析仪,对其进行在...针对串行通信过程中常用的CRC校验,在Xilinx ISE 10.1中采用IP核建立RAM,用以存入16 bit CRC校验余式表中的CRC校验码,采用VHDL语言完成了16 bit CRC校验查表法的设计。基于Xilinx公司ChipScope Pro Analyzer虚拟逻辑分析仪,对其进行在线逻辑分析,验证了设计的可行性,并在实际应用中得以实现,且表现出良好的稳定性和准确性。展开更多
A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs o...A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.展开更多
文摘针对基于光纤无线技术RoF的分布式天线系统架构,设计和实现了一种基于JEDEC的JESD207标准的射频-基带数字并行接口和Xi l i nx的高速串行Rocket IOTM技术、适用于分布式基站系统的射频-基带高速串行接口方案。该方案具有使用灵活、便于功能扩展和易于实现等特点,已用于基于RoF的无线通信实验系统。
文摘针对串行通信过程中常用的CRC校验,在Xilinx ISE 10.1中采用IP核建立RAM,用以存入16 bit CRC校验余式表中的CRC校验码,采用VHDL语言完成了16 bit CRC校验查表法的设计。基于Xilinx公司ChipScope Pro Analyzer虚拟逻辑分析仪,对其进行在线逻辑分析,验证了设计的可行性,并在实际应用中得以实现,且表现出良好的稳定性和准确性。
文摘A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.
