Fault-tolerant error-correction(FTEC)circuit is the foundation for achieving reliable quantum computation and remote communication.However,designing a fault-tolerant error correction scheme with a solid error-correcti...Fault-tolerant error-correction(FTEC)circuit is the foundation for achieving reliable quantum computation and remote communication.However,designing a fault-tolerant error correction scheme with a solid error-correction ability and low overhead remains a significant challenge.In this paper,a low-overhead fault-tolerant error correction scheme is proposed for quantum communication systems.Firstly,syndrome ancillas are prepared into Bell states to detect errors caused by channel noise.We propose a detection approach that reduces the propagation path of quantum gate fault and reduces the circuit depth by splitting the stabilizer generator into X-type and Z-type.Additionally,a syndrome extraction circuit is equipped with two flag qubits to detect quantum gate faults,which may also introduce errors into the code block during the error detection process.Finally,analytical results are provided to demonstrate the fault-tolerant performance of the proposed FTEC scheme with the lower overhead of the ancillary qubits and circuit depth.展开更多
To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable techniq...To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform.展开更多
Quantum-dot cellular automata(QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects...Quantum-dot cellular automata(QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.展开更多
In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s inter...In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates.According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61671087 and 61962009)the Fundamental Research Funds for the Central Universities,China(Grant No.2019XD-A02)+1 种基金Huawei Technologies Co.Ltd(Grant No.YBN2020085019)the Open Foundation of Guizhou Provincial Key Laboratory of Public Big Data(Grant No.2018BDKFJJ018)。
文摘Fault-tolerant error-correction(FTEC)circuit is the foundation for achieving reliable quantum computation and remote communication.However,designing a fault-tolerant error correction scheme with a solid error-correction ability and low overhead remains a significant challenge.In this paper,a low-overhead fault-tolerant error correction scheme is proposed for quantum communication systems.Firstly,syndrome ancillas are prepared into Bell states to detect errors caused by channel noise.We propose a detection approach that reduces the propagation path of quantum gate fault and reduces the circuit depth by splitting the stabilizer generator into X-type and Z-type.Additionally,a syndrome extraction circuit is equipped with two flag qubits to detect quantum gate faults,which may also introduce errors into the code block during the error detection process.Finally,analytical results are provided to demonstrate the fault-tolerant performance of the proposed FTEC scheme with the lower overhead of the ancillary qubits and circuit depth.
基金supported by the National Natural Science Foundation of China under Grant No. 60971036the National High Technology Research and Development Program of China under Grant No. 2008AA01Z104+1 种基金the Fundamental Research Funds for the Central Universities under Grant No. ZYGX2009Z004the New Century Excellent Talents in University under Grant No. NCET-08-0087
文摘To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform.
基金supported by the National Natural Science Foundation of China(No.61271122)
文摘Quantum-dot cellular automata(QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.
基金supported by the National Natural Science Foundation of China(61571149)
文摘In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates.According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.
