A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high searc...A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high search speed.Pre-layout simulation results show a 75.9% energy-delay-product（EDP） reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method.Based on this technique,a test-chip of 64-word × 144-bit ternary CAM（TCAM） is implemented using a 0.18-μm 1.8-V CMOS process,achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.展开更多
The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. A...The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status^zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.展开更多
文摘A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high search speed.Pre-layout simulation results show a 75.9% energy-delay-product（EDP） reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method.Based on this technique,a test-chip of 64-word × 144-bit ternary CAM（TCAM） is implemented using a 0.18-μm 1.8-V CMOS process,achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.
基金partially supported by the National Natural Science Foundation of China under Grant Nos.61003064,61100163,61133004,61222204,61221062,61303158the National High Technology Research and Development 863 Program of China under GrantNo.2012AA012202+1 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDA06010403the Ten Thousand Talent Program of China
文摘The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status^zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.
