A high performance 3 inch 0.5 μm InP DHBT technology with three interconnecting layers has been developed.The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required...A high performance 3 inch 0.5 μm InP DHBT technology with three interconnecting layers has been developed.The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required performances.The 0.5 × 5 μm^2 InP DHBTs demonstrated ft = 350 GHz,f（max） = 532 GHz and BV（CEO） = 4.8 V,which were modeled using Agilent-IIBT large signal model.As a benchmark circuit,a dynamic frequency divider operating from 110 to 220 GHz has been designed,fabricated and measured with this technology.The ultra-high-speed 0.5 μm InP DHBT technology offers a combination of ultra-high-speed and high breakdown voltage,which makes it an ideal candidate for next generation 100 GHz＋ mixed signal integrated circuits.展开更多
This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slav...This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.展开更多
This letter presents a high speed 2 ： 1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7μm InP DHBT technology with fTof 165 GHz and fmax of 230 GHz. The circuit includes a two-sta...This letter presents a high speed 2 ： 1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7μm InP DHBT technology with fTof 165 GHz and fmax of 230 GHz. The circuit includes a two-stage active transtbrmer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer （widely known as the Gilbert cell） and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469 × 414μm2 and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximunl output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.展开更多
A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been...A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider(with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic(DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as-20 d Bm at 32 GHz and the phase noise at 37 GHz is less than-130 d Bc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 m W at a supply voltage of 1.2 V and occupies an area of only 730 μm×475 μm.展开更多
文摘A high performance 3 inch 0.5 μm InP DHBT technology with three interconnecting layers has been developed.The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required performances.The 0.5 × 5 μm^2 InP DHBTs demonstrated ft = 350 GHz,f（max） = 532 GHz and BV（CEO） = 4.8 V,which were modeled using Agilent-IIBT large signal model.As a benchmark circuit,a dynamic frequency divider operating from 110 to 220 GHz has been designed,fabricated and measured with this technology.The ultra-high-speed 0.5 μm InP DHBT technology offers a combination of ultra-high-speed and high breakdown voltage,which makes it an ideal candidate for next generation 100 GHz＋ mixed signal integrated circuits.
基金supported by the National Basic Research Program of China(No.2010CB327404)the National Natural Science Foundation of China(No.60901012)
文摘This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.
文摘This letter presents a high speed 2 ： 1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7μm InP DHBT technology with fTof 165 GHz and fmax of 230 GHz. The circuit includes a two-stage active transtbrmer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer （widely known as the Gilbert cell） and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469 × 414μm2 and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximunl output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.
基金Project supported by the National Basic Research Program of China(No.2010CB327404)the National Natural Science Foundation of China(No.60901012)
文摘A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider(with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic(DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as-20 d Bm at 32 GHz and the phase noise at 37 GHz is less than-130 d Bc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 m W at a supply voltage of 1.2 V and occupies an area of only 730 μm×475 μm.
