As a kind of transportation mode for crossing channels, undersea tunnel has incomparable advantages for its directness, convenience, fastness, insusceptibility to weather conditions, and smaller influences on environm...As a kind of transportation mode for crossing channels, undersea tunnel has incomparable advantages for its directness, convenience, fastness, insusceptibility to weather conditions, and smaller influences on environments. In recent years, with the development of undersea tunnel construction, the design and construction technologies have been greatly enhanced. The first undersea tunnel in China has just been built. Waterproofing is the key technique of undersea tunneling. A new concept of waterproofing scheme of grouting, sealing, draining and divided sections was adopted in the construction of the tunnel based on the researches, the in-situ geological features, the astuteness of the current technology and the cost of construction. The structural details of the sealing and draining system are introduced to illustrate the salient features of the new waterproofing technique. It is hoped that experiences described in the paper can offer guidance for the construction of the extensive undersea tunnels in the coming years.展开更多
This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDL...This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDLTEFT gives the superior results with high ON state current （/ON - 0.56 mA/um）, ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing （AV-SS -- 48 mV/dec）. The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.展开更多
A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poi...A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.展开更多
In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional...In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.展开更多
In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying t...In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency（f_t）,maximum oscillation frequency（f_（max））,intrinsic gain and admittance（Y）parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current（ION）of about 0.2 mA and less leakage current（IOFF）of 29 f A is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance（g_m）,higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher f_（max） of 985 GHz is obtained for drain doping of 5×10^（17）cm^（-3） because of the reduced gate-drain capacitance（C_（gd））with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.展开更多
基金supported by the National Basic Research Program of China (973 Program,Grant No. 2010CB732104)the Fundamental Research Funds for the Central Universities (Grant No. 2011JBM133)
文摘As a kind of transportation mode for crossing channels, undersea tunnel has incomparable advantages for its directness, convenience, fastness, insusceptibility to weather conditions, and smaller influences on environments. In recent years, with the development of undersea tunnel construction, the design and construction technologies have been greatly enhanced. The first undersea tunnel in China has just been built. Waterproofing is the key technique of undersea tunneling. A new concept of waterproofing scheme of grouting, sealing, draining and divided sections was adopted in the construction of the tunnel based on the researches, the in-situ geological features, the astuteness of the current technology and the cost of construction. The structural details of the sealing and draining system are introduced to illustrate the salient features of the new waterproofing technique. It is hoped that experiences described in the paper can offer guidance for the construction of the extensive undersea tunnels in the coming years.
文摘This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDLTEFT gives the superior results with high ON state current （/ON - 0.56 mA/um）, ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing （AV-SS -- 48 mV/dec）. The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.
基金Project supported by the National Natural Science Foundation of China(No.61376106)the Graduate Innovation Fund of Anhui University
文摘A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176038 and 61474093)the Science and Technology Planning Project of Guangdong Province,China(Grant No.2015A010103002)the Technology Development Program of Shanxi Province,China(Grant No.2016GY075)
文摘In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.
基金Project supported by the Department of Science and Technology,Government of India under SERB Scheme(No.SERB/F/2660)
文摘In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency（f_t）,maximum oscillation frequency（f_（max））,intrinsic gain and admittance（Y）parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current（ION）of about 0.2 mA and less leakage current（IOFF）of 29 f A is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance（g_m）,higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher f_（max） of 985 GHz is obtained for drain doping of 5×10^（17）cm^（-3） because of the reduced gate-drain capacitance（C_（gd））with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.
