Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pa...Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pacitor size. In this paper, a small size three-dimensional （3-D） metal-oxide-metal （MOM） capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that 1NL is less than -4-1 LSB and DNL is less than ＋0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.展开更多
文摘Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pacitor size. In this paper, a small size three-dimensional （3-D） metal-oxide-metal （MOM） capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that 1NL is less than -4-1 LSB and DNL is less than ＋0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.
