A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also pro...A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.展开更多
Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. T...Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.展开更多
文章分别介绍了基于查找表法和CORDIC(COordination Rotation DIgital Computer)法实现的数控振荡器的优点和缺点,并推导了CORDIC算法产生正余弦信号的实现过程。综合它们各自的优点,实现一种混合算法的数控振荡器,最后将其运用FPGA技...文章分别介绍了基于查找表法和CORDIC(COordination Rotation DIgital Computer)法实现的数控振荡器的优点和缺点,并推导了CORDIC算法产生正余弦信号的实现过程。综合它们各自的优点,实现一种混合算法的数控振荡器,最后将其运用FPGA技术实现。Modelsim和quartusⅡ仿真和验证结果表明,此设计是可行的,并且易于FPGA实现。与仅仅基于查找表法实现的NCO相比,其结构更简单,精度高,耗费资源少,速度快。展开更多
文摘A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.
文摘Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.
文摘文章分别介绍了基于查找表法和CORDIC(COordination Rotation DIgital Computer)法实现的数控振荡器的优点和缺点,并推导了CORDIC算法产生正余弦信号的实现过程。综合它们各自的优点,实现一种混合算法的数控振荡器,最后将其运用FPGA技术实现。Modelsim和quartusⅡ仿真和验证结果表明,此设计是可行的,并且易于FPGA实现。与仅仅基于查找表法实现的NCO相比,其结构更简单,精度高,耗费资源少,速度快。
