为了实现较高的电容检测范围,传统的采用SAR ADC的开关电容(Switched capacitor,SC)的电容数字转换器(Capacitance to digital converter,CDC)使用高压供电提高输出摆幅,而其为了保证噪声性能又采用大电流驱动,所以显著增加了系统功耗...为了实现较高的电容检测范围,传统的采用SAR ADC的开关电容(Switched capacitor,SC)的电容数字转换器(Capacitance to digital converter,CDC)使用高压供电提高输出摆幅,而其为了保证噪声性能又采用大电流驱动,所以显著增加了系统功耗。为了解决以上问题,提出了一种基于数字放大器的电容数字转换器,将CDAC阵列作为模拟输出承担高压。仅对CDAC阵列与传感电容采用高压(5 V)驱动,而其余部分仍采用低压(1 V)供电,使得CDC在达到高动态范围与高灵敏度的同时保持低功耗、低噪声。此外,针对噪声的优化,本文一方面通过在数字放大器内加入积分环路实现SAR ADC的一阶噪声整形,降低了系统的量化噪声,提高了CDC的有效位数;另一方面通过引入有源噪声抵消(Active noise cancellation technology,ANC)技术,降低了系统的混叠噪声,提高了系统的信噪比。展开更多
随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优...随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。展开更多
A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplif...A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier （IA） and a cyclic analog-to-digital converter （CADC）. The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits （ENOB） of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 （including pads）. In-vitro recording was successfully carried out by the proposed frontend chip.展开更多
文摘考虑到弹光调制技术PEM(photo-elastic modulation)测量光学旋光高灵敏度、高精度的优点,设计了一种基于PEM的软硬件相互配合的旋光数据解调系统,以满足实时稳定的旋光角度测量要求。在FPGA内使用多通道直接数字频率合成技术DDS(Direct Digital Synthesis),采用同一频率控制字产生PEM的驱动信号和数字锁相的倍频参考信号,保证了信号的同频同源。弹光调制信号的交流序列和直流序列分别通过两路串口设备并行传输,Lab VIEW完成串口资源配置和数据缓存,经数字锁相解调得到光学旋光角度。实验表明,在旋光角为8.52×10(-5)rad时,系统的标准偏差是1.48×10^(-6)rad。
文摘近年来,深度学习(Deep Learning,DL)在通信场景中的应用逐渐兴起,其中就包括射频发射机的数字预失真(Digital Predistortion,DPD)处理。然而,由于射频功率放大器(Power Amplifier,PA)固有的非线性失真和记忆效应特点,如果直接应用传统DL算法去实现DPD会出现拟合效果不佳、自适应性差等现象。针对这个问题,本文提出了一种由多智能体反馈神经网络实现的数字预失真器(Multi-Agent Feedback Enabled Neural Network for Digital Predistortion,MAFENN-DPD),该网络引入了具有高纠错能力的反馈智能体结构,其主要特点是基于Stackelberg博弈理论去加速网络训练和收敛,同时我们还应用信息瓶颈理论指导网络超参数设计以增强MAFENN-DPD对PA记忆效应变化的动态适应能力。我们进行了一系列的实验来验证MAFENN-DPD的有效性。与使用典型前馈网络实现的DPD方案相比,基于MAFENN-DPD的方案在相邻信道功率比(Adjacent Channel Power Ratio,ACPR)指标上提高了约5 dB。同时,在没有通信过程中的大量先验知识的情况下,MAFENN-DPD实现了与使用记忆多项式方法建模的DPD方案十分接近的ACPR性能。仿真结果说明MAFENN-DPD相比传统神经网络可进一步提升ACPR性能,同时相比记忆多项式方法具有更好的自适应建模能力和通用性,并且具有多智能体反馈结构特征的神经网络未来在其他的通信场景中也具有应用推广的潜力。
文摘随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。
基金Project supported by the National Natural Science Foundation of China(Nos.61474107,61372060,61335010,61275200,61178051)the Key Program of the Chinese Academy of Sciences(No.KJZD-EW-L11-01)
文摘A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier （IA） and a cyclic analog-to-digital converter （CADC）. The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits （ENOB） of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 （including pads）. In-vitro recording was successfully carried out by the proposed frontend chip.
