Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a...Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.展开更多
Domestic off-grid renewable energy systems have become common place in many areas of the world, as humanity seeks to keep abreast with global technological changes and advancements. This paper aims to present a cost-e...Domestic off-grid renewable energy systems have become common place in many areas of the world, as humanity seeks to keep abreast with global technological changes and advancements. This paper aims to present a cost-effective energy monitoring system which may be used to analyze and evaluate the operation of a domestic off-grid PV system. Parameters which are monitored include the output voltage and current from a 55 W polycrystalline PV panel. The output voltage and current from a power regulation circuit (which could be a DC-DC converter, solar charger or MPPT) is also monitored with this singular system which incorporates a data logging interface circuit, a data logger and a personal computer.展开更多
This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplif...This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA). The proposed filter provides the following important and desirable features: (i) One can use only one CCDDCCTA and two capacitors;(ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses from the same configuration without any alteration;(iii) Passive components are grounded, which ease the integrated circuit implementation;(iv) Responses are electronically tunable;and (v) Sensitivity is low. Moreover, the non-ideality analysis shows that the parasitic passive components can be compensated for the proposed circuit. The functionality of the design is verified through SPICE simulations using 0.25 μm CMOS TSMC technology process parameters. Simulation result agrees well with the theoretical analysis.展开更多
This work presents a novel current-mode (CM) lossless integrator that uses one current differencing differential input transconductance amplifier (CDDITA) and one grounded capacitor. The configuration based on single ...This work presents a novel current-mode (CM) lossless integrator that uses one current differencing differential input transconductance amplifier (CDDITA) and one grounded capacitor. The configuration based on single active element has several advantages from the aspect of monolithic integration, few are: reduced power consumption, chip miniaturization. Employment of grounded capacitor is also beneficial for monolithic integration. Specifying some of the key features of integrator proposed are: 1) purely resistorless, 2) electronically tunable, 3) current output available at the port having high impedance, and 4) excellent performance under non-ideal conditions. So, a resister-less current mode lossy integrator with electronic control employing single CDDITA has been proposed in this paper. The verification of workability of the proposed current mode integrator is well explained by the help of SPICE simulations using TSMC CMOS 0.18 μm technology node.展开更多
基金Research General Direction funded this research at Universidad Santiago de Cali,Grant Number 01-2021 and APC was funded by 01-2021.
文摘Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.
文摘Domestic off-grid renewable energy systems have become common place in many areas of the world, as humanity seeks to keep abreast with global technological changes and advancements. This paper aims to present a cost-effective energy monitoring system which may be used to analyze and evaluate the operation of a domestic off-grid PV system. Parameters which are monitored include the output voltage and current from a 55 W polycrystalline PV panel. The output voltage and current from a power regulation circuit (which could be a DC-DC converter, solar charger or MPPT) is also monitored with this singular system which incorporates a data logging interface circuit, a data logger and a personal computer.
文摘This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA). The proposed filter provides the following important and desirable features: (i) One can use only one CCDDCCTA and two capacitors;(ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses from the same configuration without any alteration;(iii) Passive components are grounded, which ease the integrated circuit implementation;(iv) Responses are electronically tunable;and (v) Sensitivity is low. Moreover, the non-ideality analysis shows that the parasitic passive components can be compensated for the proposed circuit. The functionality of the design is verified through SPICE simulations using 0.25 μm CMOS TSMC technology process parameters. Simulation result agrees well with the theoretical analysis.
文摘This work presents a novel current-mode (CM) lossless integrator that uses one current differencing differential input transconductance amplifier (CDDITA) and one grounded capacitor. The configuration based on single active element has several advantages from the aspect of monolithic integration, few are: reduced power consumption, chip miniaturization. Employment of grounded capacitor is also beneficial for monolithic integration. Specifying some of the key features of integrator proposed are: 1) purely resistorless, 2) electronically tunable, 3) current output available at the port having high impedance, and 4) excellent performance under non-ideal conditions. So, a resister-less current mode lossy integrator with electronic control employing single CDDITA has been proposed in this paper. The verification of workability of the proposed current mode integrator is well explained by the help of SPICE simulations using TSMC CMOS 0.18 μm technology node.
