Circuit design of 32 bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure cost...Circuit design of 32 bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than ELM.At circuit level,a carry incorporating structure to include the primary carry input in carry chain and an 'and xor' structure to implement final sum logic in 32 bit LSA are designed for better optimization.For 5V,1μm process,32 bit LSA has a critical delay of 5 9ns and costs an area of 0 62mm 2,power consumption of 23mW at 100MHz.For 2 5V,0 25μm process,critical delay of 0 8ns,power dissipation of 5 2mW at 100MHz is simulated.展开更多
Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low...Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high e...Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high energy dissipation are some of the concerns.Quantum-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS.The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate structures.This paper represents scalable 1-bit QCA full adder structures based on cell interaction.Our proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area occupation.Also,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array multiplier.All designs were simulated and verified using QCA Designer-E version 2.2.This tool can estimate the energy dissipation as well as evaluate the performance of the circuits.Simulation results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.展开更多
量子全加器是量子计算机的基本单元,为了减少能耗,降低构造成本及物理实现难度,本文提出一种新型 n 位量子全加器,使用 3n 个CNOT(Controlled NOT)门和 2n -1个Toffoli门实现 n 位量子加减法,采用超前进位方式,不含进位输入,通过最高溢...量子全加器是量子计算机的基本单元,为了减少能耗,降低构造成本及物理实现难度,本文提出一种新型 n 位量子全加器,使用 3n 个CNOT(Controlled NOT)门和 2n -1个Toffoli门实现 n 位量子加减法,采用超前进位方式,不含进位输入,通过最高溢出标志位判断加法的进位和减法的正负号,标志位不参与高低位计算,不增加电路延时,适合 n 位量子并行计算.随机生成4、8、16和32位数分别进行加减仿真操作,验证了全加器的正确性.该全加器量子代价较低,结构简单,有利于提高集成电路规模和集成度.展开更多
文摘Circuit design of 32 bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than ELM.At circuit level,a carry incorporating structure to include the primary carry input in carry chain and an 'and xor' structure to implement final sum logic in 32 bit LSA are designed for better optimization.For 5V,1μm process,32 bit LSA has a critical delay of 5 9ns and costs an area of 0 62mm 2,power consumption of 23mW at 100MHz.For 2 5V,0 25μm process,critical delay of 0 8ns,power dissipation of 5 2mW at 100MHz is simulated.
文摘Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.
文摘Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high energy dissipation are some of the concerns.Quantum-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS.The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate structures.This paper represents scalable 1-bit QCA full adder structures based on cell interaction.Our proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area occupation.Also,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array multiplier.All designs were simulated and verified using QCA Designer-E version 2.2.This tool can estimate the energy dissipation as well as evaluate the performance of the circuits.Simulation results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.
文摘量子全加器是量子计算机的基本单元,为了减少能耗,降低构造成本及物理实现难度,本文提出一种新型 n 位量子全加器,使用 3n 个CNOT(Controlled NOT)门和 2n -1个Toffoli门实现 n 位量子加减法,采用超前进位方式,不含进位输入,通过最高溢出标志位判断加法的进位和减法的正负号,标志位不参与高低位计算,不增加电路延时,适合 n 位量子并行计算.随机生成4、8、16和32位数分别进行加减仿真操作,验证了全加器的正确性.该全加器量子代价较低,结构简单,有利于提高集成电路规模和集成度.
