This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the ...This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the difficulty of asynchronous design and performance analysis, both complete asynchronous and partial asynchronous structures aere designed and compared. Results of comparison with the well-Rnown industrial product ARM922T verify that about 30% and 40% performance improvement of the partiM and complete asynchronous complex pipelines can be obtained respectively. The design methodologies can also be used in the design of other asynchronous pipelines.展开更多
It is important to verify the absence of deadlocks in asynchronous circuits. Much previous work relies on a reachability analysis of the circuits＇ states, with the use of binary decision diagrams （BDDs） or Petri ne...It is important to verify the absence of deadlocks in asynchronous circuits. Much previous work relies on a reachability analysis of the circuits＇ states, with the use of binary decision diagrams （BDDs） or Petri nets to model the behaviors of circuits. This paper presents an alternative approach focusing on the structural properties of well-formed asynchronous circuits that will never suffer deadlocks. A class of data-driven asynchronous pipelines is targeted in this paper, which can be viewed as a network of basic components connected by handshake channels. The sufficient and necessary conditions for a component network consisting of Steer, Merge, Fork and Join are given. The slack elasticity of the channels is analyzed in order to introduce pipelining. As an application, a deadlock checking method is implemented in a syntax-directed asynchronous design tool Team The proposed method shows a great runtime advantage when compared against previous Petri net based verification tools.展开更多
随着信息化社会的深入发展,数字集成电路技术运用得越来越广泛.乘法器是数字电路系统最重要的算术运算单元之一,影响了整个电路系统的工作效率.实际设计通常采用Booth结构作为数字乘法器实现框架,决定此类乘法器运算效率的最为关键的两...随着信息化社会的深入发展,数字集成电路技术运用得越来越广泛.乘法器是数字电路系统最重要的算术运算单元之一,影响了整个电路系统的工作效率.实际设计通常采用Booth结构作为数字乘法器实现框架,决定此类乘法器运算效率的最为关键的两个方面是:部分积产生和部分积合并.提出了一种从结构上采用独立路由寻址的机制来实现部分积的产生,设计方法上采用异步微流水线,控制机制上采取数据通路的方法,来设计基于异步NoC(Network On Chip)机制的Booth乘法器设计.最后,通过FPGA开发板进行了仿真和实现,并与传统的Booth乘法器性能做了对比分析.展开更多
As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scalin...As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance.In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding,spanning different handshake signaling protocols such as 2-phase(micropipeline, Mousetrap, and Click), 4-phase(simple, semi-decoupled, and fully-decoupled), and single-track(GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.展开更多
To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S...To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. （1） Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. （2） Operations of latches were controlled by latch controllers based on presented asynchronous sequence element： LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. （3） Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor （CMOS） process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty （ 11.7% ） compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property （IP） embedded in the targeted systems such as wireless sensor networks （WSN）, smart-cards and radio frequency identification （RFID）.展开更多
基金the Research Project of China Military Department (No. 6130325)
文摘This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the difficulty of asynchronous design and performance analysis, both complete asynchronous and partial asynchronous structures aere designed and compared. Results of comparison with the well-Rnown industrial product ARM922T verify that about 30% and 40% performance improvement of the partiM and complete asynchronous complex pipelines can be obtained respectively. The design methodologies can also be used in the design of other asynchronous pipelines.
基金supported by the National Natural Science Foundation of China under Grant Nos.60873015,61070037,and 61103016
文摘It is important to verify the absence of deadlocks in asynchronous circuits. Much previous work relies on a reachability analysis of the circuits＇ states, with the use of binary decision diagrams （BDDs） or Petri nets to model the behaviors of circuits. This paper presents an alternative approach focusing on the structural properties of well-formed asynchronous circuits that will never suffer deadlocks. A class of data-driven asynchronous pipelines is targeted in this paper, which can be viewed as a network of basic components connected by handshake channels. The sufficient and necessary conditions for a component network consisting of Steer, Merge, Fork and Join are given. The slack elasticity of the channels is analyzed in order to introduce pipelining. As an application, a deadlock checking method is implemented in a syntax-directed asynchronous design tool Team The proposed method shows a great runtime advantage when compared against previous Petri net based verification tools.
文摘随着信息化社会的深入发展,数字集成电路技术运用得越来越广泛.乘法器是数字电路系统最重要的算术运算单元之一,影响了整个电路系统的工作效率.实际设计通常采用Booth结构作为数字乘法器实现框架,决定此类乘法器运算效率的最为关键的两个方面是:部分积产生和部分积合并.提出了一种从结构上采用独立路由寻址的机制来实现部分积的产生,设计方法上采用异步微流水线,控制机制上采取数据通路的方法,来设计基于异步NoC(Network On Chip)机制的Booth乘法器设计.最后,通过FPGA开发板进行了仿真和实现,并与传统的Booth乘法器性能做了对比分析.
基金supported in part by the Hainan Academician Innovation Platform (No. YSPTZX202036)in part by the Hainan Natural Science Foundation (No. 619MS054)。
文摘As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance.In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding,spanning different handshake signaling protocols such as 2-phase(micropipeline, Mousetrap, and Click), 4-phase(simple, semi-decoupled, and fully-decoupled), and single-track(GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.
基金the National High Technology Research and Development Programme of China(Grant No2006AA01Z226)the Project(Grant No2006Z001B)the Scientific Research Foundation of Huazhong University of Science and Technology
文摘To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. （1） Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. （2） Operations of latches were controlled by latch controllers based on presented asynchronous sequence element： LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. （3） Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor （CMOS） process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty （ 11.7% ） compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property （IP） embedded in the targeted systems such as wireless sensor networks （WSN）, smart-cards and radio frequency identification （RFID）.
