Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
Efficient quantum circuits for arithmetic operations are vital for quantum algorithms.A fault-tolerant circuit is required for a robust quantum computing in the presence of noise.Quantum circuits based on Clifford+T g...Efficient quantum circuits for arithmetic operations are vital for quantum algorithms.A fault-tolerant circuit is required for a robust quantum computing in the presence of noise.Quantum circuits based on Clifford+T gates are easily rendered faulttolerant.Therefore,reducing the T-depth and T-Count without increasing the qubit number represents vital optimization goals for quantum circuits.In this study,we propose the fault-tolerant implementations for TR and Peres gates with optimized T-depth and T-Count.Next,we design fault-tolerant circuits for quantum arithmetic operations using the TR and Peres gates.Then,we implement cyclic and complete translations of quantum images using quantum arithmetic operations,and the scalar matrix multiplication.Comparative analysis and simulation results reveal that the proposed arithmetic and image operations are efficient.For instance,cyclic translations of a quantum image produce 50%T-depth reduction relative to the previous best-known cyclic translation.展开更多
An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications wi...An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZDIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.展开更多
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
基金supported by the National Natural Science Foundation of China(Grant Nos.61762012,and 61763014)the Science and Technology Project of Guangxi(Grant No.2018JJA170083)+3 种基金the National Key Research and Development Plan(Grant Nos.2018YFC1200200,and 2018YFC1200205)the Fund for Distinguished Young Scholars of Jiangxi Province(Grant No.2018ACB2101)the Natural Science Foundation of Jiangxi Province of China(Grant No.20192BAB207014)the Science and Technology Research Project of Jiangxi Provincial Education Department(Grant No.GJJ190297)。
文摘Efficient quantum circuits for arithmetic operations are vital for quantum algorithms.A fault-tolerant circuit is required for a robust quantum computing in the presence of noise.Quantum circuits based on Clifford+T gates are easily rendered faulttolerant.Therefore,reducing the T-depth and T-Count without increasing the qubit number represents vital optimization goals for quantum circuits.In this study,we propose the fault-tolerant implementations for TR and Peres gates with optimized T-depth and T-Count.Next,we design fault-tolerant circuits for quantum arithmetic operations using the TR and Peres gates.Then,we implement cyclic and complete translations of quantum images using quantum arithmetic operations,and the scalar matrix multiplication.Comparative analysis and simulation results reveal that the proposed arithmetic and image operations are efficient.For instance,cyclic translations of a quantum image produce 50%T-depth reduction relative to the previous best-known cyclic translation.
基金the National Natural Science Foundation of China (No. 90207002)
文摘An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZDIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.
