在传统对称式电阻、电容、二极管RCD(resistance capacitance diode)箝位正激变换器基础上,通过引入中间电容和用开关管代替副边的一个二极管,提出了一种具有正反激功能的新型变换器。该变换器在继承传统对称式RCD箝位正-反激变换器的...在传统对称式电阻、电容、二极管RCD(resistance capacitance diode)箝位正激变换器基础上,通过引入中间电容和用开关管代替副边的一个二极管,提出了一种具有正反激功能的新型变换器。该变换器在继承传统对称式RCD箝位正-反激变换器的高效率、占空比可大于0.5和低开关管电压应力优点的同时,进一步拓宽输入电压变化范围和提高输出电压增益。首先分析了变换器工作于激磁电流连续导电模式MCCM(magnetizing current continuous mode)的工作过程,详细分析了MCCM和激磁电流断续导电模式MDCM(magnetizing current discontinuous mode)2种模式下的宽范围和增益特性以及原/副边开关管实现零电压转换ZVS(zero voltage switch)的条件;然后确立了在一定漏电感功率下箝位电阻值与箝位电容电压之间的函数关系曲线,并以此作为选取箝位电阻参考。最后,通过一台实验样机验证了理论分析的正确性。展开更多
A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend bot...A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend both the signal input range and the tuning capability. The effective transconductance of the body-driven triode stage is increased using a partial positive feedback technique which also partially solves the problem introduced by the small transconductance. This design uses the UMC 0.18 μm CMOS process. Simulations show the transconductor operated with 1 V supply voltage has less than -55 dB total harmonic distortions （THD） in the complete tuning range （0 V≤ Vcont≤ 0.43 V） for a 1 MHz 0.8 Vp-p differential input. The power consumption is 70 μW for a 0.43 V control voltage.展开更多
文摘在传统对称式电阻、电容、二极管RCD(resistance capacitance diode)箝位正激变换器基础上,通过引入中间电容和用开关管代替副边的一个二极管,提出了一种具有正反激功能的新型变换器。该变换器在继承传统对称式RCD箝位正-反激变换器的高效率、占空比可大于0.5和低开关管电压应力优点的同时,进一步拓宽输入电压变化范围和提高输出电压增益。首先分析了变换器工作于激磁电流连续导电模式MCCM(magnetizing current continuous mode)的工作过程,详细分析了MCCM和激磁电流断续导电模式MDCM(magnetizing current discontinuous mode)2种模式下的宽范围和增益特性以及原/副边开关管实现零电压转换ZVS(zero voltage switch)的条件;然后确立了在一定漏电感功率下箝位电阻值与箝位电容电压之间的函数关系曲线,并以此作为选取箝位电阻参考。最后,通过一台实验样机验证了理论分析的正确性。
文摘基于HHNEC BCD工艺,设计了一种输入电压范围为5.4-40 V,输出电压为5 V的线性稳压器。为了获得高电源电压抑制比,电路采用二级稳压结构,基于耗尽型MOS管的预稳压器将输入电压稳压到5.2 V,再使用一种输出端接2.2μF电容的低压差稳压器（二次稳压器）得到最终输出电压5 V。Hspice仿真表明,PSRR在100 k Hz以下时优于-90 d B,在1 MHz以下时优于-70 d B。
文摘A CMOS triode transconductor was developed with common mode feedback suitable for operating in low-voltage and low-power applications. The design is based on a body-driven input stage with feedback loops to extend both the signal input range and the tuning capability. The effective transconductance of the body-driven triode stage is increased using a partial positive feedback technique which also partially solves the problem introduced by the small transconductance. This design uses the UMC 0.18 μm CMOS process. Simulations show the transconductor operated with 1 V supply voltage has less than -55 dB total harmonic distortions （THD） in the complete tuning range （0 V≤ Vcont≤ 0.43 V） for a 1 MHz 0.8 Vp-p differential input. The power consumption is 70 μW for a 0.43 V control voltage.
