The cost of the central register file and the size of the program code limit the scalability of very long instruction word（VLIW） processors with increasing numbers of functional units.This paper presents the archite...The cost of the central register file and the size of the program code limit the scalability of very long instruction word（VLIW） processors with increasing numbers of functional units.This paper presents the architectural design of a six-way VLIW digital signal processor（DSP） with clustered register files.The architecture uses a variable length instruction set and supports dynamic instruction dispatching.The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM.A compiler based on the Open64 was developed for the system.Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.展开更多
针对传统超长指令字(Very Long Instruction Word,VLIW)处理器代码体积增大会显著降低处理器性能的问题,设计了一种八流出新型变长指令跨边界派发窗。该派发窗兼容压缩指令派发功能,支持压缩指令和整字指令混合派发,有效减小了处理器代...针对传统超长指令字(Very Long Instruction Word,VLIW)处理器代码体积增大会显著降低处理器性能的问题,设计了一种八流出新型变长指令跨边界派发窗。该派发窗兼容压缩指令派发功能,支持压缩指令和整字指令混合派发,有效减小了处理器代码体积。同时该派发窗引入指令跨边界派发机制,进一步排出指令间无用气泡。通过搭建派发窗仿真模型,并基于DSP/VoLIB库进行仿真,结果显示,采用新型变长指令跨边界派发窗能够充分发挥指令级并行优势。经编译器调度优化后,库中典型程序体积比传统派发窗平均降低约19.26%,处理器性能提升约15.4%。展开更多
Very Long Instruction Word （VLIW） architectures are commonly used in application-specific domains due to their parallelism and low-power characteristics. Recently, parameterization of such architectures allows for r...Very Long Instruction Word （VLIW） architectures are commonly used in application-specific domains due to their parallelism and low-power characteristics. Recently, parameterization of such architectures allows for runtime adaptation of the issue-width to match the inherent Instruction Level Parallelism （ILP） of an application. One implementation of such an approach is that the event of the issue-width switching dynamically triggers the reconfiguration of the data cache at runtime. In this paper, the relationship between cache resizing and issue-width is well investigated. We have observed that the requirement of the cache does not always correlate with the issue- width of the VLIW processor. To further coordinate the cache resizing with the changing issue-width, we present a novel feedback mechanism to ＂block＂ the low yields of cache resizing when the issue-width changes. In this manner, our feedback cache mechanism has a coordinated effort with the issue-width changes, which leads to a noticeable improvement of the cache performance. The experiments show that there is 10% energy savings as well as a 2.3% cache misses decline on average achieved, compared with the cache without the feedback mechanism. Therefore, the feedback mechanism is proven to have the capability to ensure more benefits are achieved from the dynamic and frequent reconfiguration.展开更多
指令压缩技术能够克服传统超长指令字(very long instruction word,VLIW)结构的指令高速缓冲(cache)中长指令字密度低的缺陷,使长指令字中的各条指令能紧密地排列在高速缓冲行(cache line)中,但可能导致长指令字分置于两个cache line,...指令压缩技术能够克服传统超长指令字(very long instruction word,VLIW)结构的指令高速缓冲(cache)中长指令字密度低的缺陷,使长指令字中的各条指令能紧密地排列在高速缓冲行(cache line)中,但可能导致长指令字分置于两个cache line,使其不能同时参与取指与发射,从而成为处理器的性能瓶颈.受到分置cache line的影响,传统提升循环效率的软件流水方法性能下降.高性能变长指令发射窗的机制能够解决分离指令字带来的取指发射问题,为取指流水线提供高效连续的指令流,特别地,该机制缓存循环的一次迭代,硬件支持循环的软件流水,有效地增强VLIW结构的数字信号处理器(digital signal processor,DSP)的性能.通过搭建时钟精确的处理器仿真模型,并基于DSP?IMG库上进行仿真,结果显示,采用两级指令发射窗机制,平均性能提高约21.89%.展开更多
Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Th...Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Thace Software Pipelining,targeted to the instruction-level parallel processors such as Very Long Instruc-tion Word (VLIW) and superscalar machines. Thace software pipelining applies a global code scheduling technique to compact the original loop body. The re-sulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or call be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promis-ing in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.展开更多
As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm t...As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word （VLIW） architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based （Directed Acyclic Graph） leakage-aware scheduling algorithm.展开更多
Matrix inversion is a critical part in communication, signal processing and electromagnetic system. A flexible and scalable very long instruction word （VLIW） processor with clustered architecture is proposed for mat...Matrix inversion is a critical part in communication, signal processing and electromagnetic system. A flexible and scalable very long instruction word （VLIW） processor with clustered architecture is proposed for matrix inversion. A global register file （RF） is used to connect al the clusters. Two nearby clusters share a local register file. The instruction sets are also designed for the VLIW processor. Experimental results show that the proposed VLIW architecture takes only 45 latency to invert a 4 × 4 matrix when running at 150 MHz. The proposed design is roughly five times faster than the DSP solution in processing speed.展开更多
基金Supported by the National Natural Science Foundation of China (No.60236020)the Specialized Research Fund for the Doctoral Program of Higher Education of MOE,China (No.20050003083)
文摘The cost of the central register file and the size of the program code limit the scalability of very long instruction word（VLIW） processors with increasing numbers of functional units.This paper presents the architectural design of a six-way VLIW digital signal processor（DSP） with clustered register files.The architecture uses a variable length instruction set and supports dynamic instruction dispatching.The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM.A compiler based on the Open64 was developed for the system.Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.
文摘针对传统超长指令字(Very Long Instruction Word,VLIW)处理器代码体积增大会显著降低处理器性能的问题,设计了一种八流出新型变长指令跨边界派发窗。该派发窗兼容压缩指令派发功能,支持压缩指令和整字指令混合派发,有效减小了处理器代码体积。同时该派发窗引入指令跨边界派发机制,进一步排出指令间无用气泡。通过搭建派发窗仿真模型,并基于DSP/VoLIB库进行仿真,结果显示,采用新型变长指令跨边界派发窗能够充分发挥指令级并行优势。经编译器调度优化后,库中典型程序体积比传统派发窗平均降低约19.26%,处理器性能提升约15.4%。
基金supported by the National Natural Science Foundation of China(Nos.61300010 and 61300011)
文摘Very Long Instruction Word （VLIW） architectures are commonly used in application-specific domains due to their parallelism and low-power characteristics. Recently, parameterization of such architectures allows for runtime adaptation of the issue-width to match the inherent Instruction Level Parallelism （ILP） of an application. One implementation of such an approach is that the event of the issue-width switching dynamically triggers the reconfiguration of the data cache at runtime. In this paper, the relationship between cache resizing and issue-width is well investigated. We have observed that the requirement of the cache does not always correlate with the issue- width of the VLIW processor. To further coordinate the cache resizing with the changing issue-width, we present a novel feedback mechanism to ＂block＂ the low yields of cache resizing when the issue-width changes. In this manner, our feedback cache mechanism has a coordinated effort with the issue-width changes, which leads to a noticeable improvement of the cache performance. The experiments show that there is 10% energy savings as well as a 2.3% cache misses decline on average achieved, compared with the cache without the feedback mechanism. Therefore, the feedback mechanism is proven to have the capability to ensure more benefits are achieved from the dynamic and frequent reconfiguration.
文摘指令压缩技术能够克服传统超长指令字(very long instruction word,VLIW)结构的指令高速缓冲(cache)中长指令字密度低的缺陷,使长指令字中的各条指令能紧密地排列在高速缓冲行(cache line)中,但可能导致长指令字分置于两个cache line,使其不能同时参与取指与发射,从而成为处理器的性能瓶颈.受到分置cache line的影响,传统提升循环效率的软件流水方法性能下降.高性能变长指令发射窗的机制能够解决分离指令字带来的取指发射问题,为取指流水线提供高效连续的指令流,特别地,该机制缓存循环的一次迭代,硬件支持循环的软件流水,有效地增强VLIW结构的数字信号处理器(digital signal processor,DSP)的性能.通过搭建时钟精确的处理器仿真模型,并基于DSP?IMG库上进行仿真,结果显示,采用两级指令发射窗机制,平均性能提高约21.89%.
文摘Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Thace Software Pipelining,targeted to the instruction-level parallel processors such as Very Long Instruc-tion Word (VLIW) and superscalar machines. Thace software pipelining applies a global code scheduling technique to compact the original loop body. The re-sulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or call be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promis-ing in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.
基金supported by the National Natural Science Foundation of China under Grant Nos. 60873006 and 61070049the International Collaborative Research Program under Grant No. 2010DFB10930+1 种基金the Beijing Science Foundation under Grant No.KZ200910028007the Australian Research Council (ARC) under Grant No. DP0881330
文摘As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word （VLIW） architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based （Directed Acyclic Graph） leakage-aware scheduling algorithm.
基金supported by the National Natural Science Foundation of China(6110015561227004+4 种基金613720716137213161201289)the Fundamental Research Funds of the Central Universities of China(K5051302096JB140207)
文摘Matrix inversion is a critical part in communication, signal processing and electromagnetic system. A flexible and scalable very long instruction word （VLIW） processor with clustered architecture is proposed for matrix inversion. A global register file （RF） is used to connect al the clusters. Two nearby clusters share a local register file. The instruction sets are also designed for the VLIW processor. Experimental results show that the proposed VLIW architecture takes only 45 latency to invert a 4 × 4 matrix when running at 150 MHz. The proposed design is roughly five times faster than the DSP solution in processing speed.
