在不追加额外的硬件设备投资的前提下,提升直流输电系统的抑制连续换相失败的能力具有重要意义;为此,首先阐述了基于电网换相的直流输电系统换流器换相机理,分析了低压限流启动(VDCOL,voltage dependent current order limiter)的控制方...在不追加额外的硬件设备投资的前提下,提升直流输电系统的抑制连续换相失败的能力具有重要意义;为此,首先阐述了基于电网换相的直流输电系统换流器换相机理,分析了低压限流启动(VDCOL,voltage dependent current order limiter)的控制方法,并根据实时测量的换流母线电压VDCOL的启动电压替代常规的直流电压测量,得到系统故障期间变化缓慢的启动电压;其次基于正常换相机理分析,改变常规VDCOL直流电压与直流电流之间的线性静态恢复关系,将VDCOL常规控制模型替换为变斜率数学模型,再将计算得到的VDCOL启动电压与变斜率VDCOL相结合;最后基于CIGRE HVDC(Conference International des Grands Reseaux Electriques,High-Voltage Direct Current Transmissions)标准测试模型验证了本文提出的控制策略在抑制连续换相失败方面具有明显的有效性与优越性。展开更多
This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled g...This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.展开更多
文摘在不追加额外的硬件设备投资的前提下,提升直流输电系统的抑制连续换相失败的能力具有重要意义;为此,首先阐述了基于电网换相的直流输电系统换流器换相机理,分析了低压限流启动(VDCOL,voltage dependent current order limiter)的控制方法,并根据实时测量的换流母线电压VDCOL的启动电压替代常规的直流电压测量,得到系统故障期间变化缓慢的启动电压;其次基于正常换相机理分析,改变常规VDCOL直流电压与直流电流之间的线性静态恢复关系,将VDCOL常规控制模型替换为变斜率数学模型,再将计算得到的VDCOL启动电压与变斜率VDCOL相结合;最后基于CIGRE HVDC(Conference International des Grands Reseaux Electriques,High-Voltage Direct Current Transmissions)标准测试模型验证了本文提出的控制策略在抑制连续换相失败方面具有明显的有效性与优越性。
文摘This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.
