A new method of measuring the icing thickness of transmission lines on-line is proposed in this paper.In this method,the pictures of transmission lines which are photoed by the camera on the iron tower are processed i...A new method of measuring the icing thickness of transmission lines on-line is proposed in this paper.In this method,the pictures of transmission lines which are photoed by the camera on the iron tower are processed immediately to extract the edges of the transmission line conductor and transmission line insulators.The icing thickness can be gained by comparing the edges of the iced transmission line and the uniced one.Two icing image edge extraction methods are described in detail,that is,a method based on the combination of the wavelet transform and the floating threshold method and a method based on the combination of the optimal threshold method and the mathematical morphology transform.The icing images from the artificial climatic chamber and transmission lines are used to test the methods above.The results show that the method based on the wavelet transform and the floating threshold method does well in the extraction of relatively smooth edges,such as glaze icing on conductor and icing on the insulator;meanwhile,the method based on the optimal threshold method and the mathematical morphology transform does well in the edge extraction of icing on the conductor,especially the opaque rime icing on the conductor with complicated edges.展开更多
A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported. The characteristics of both devices are observed as varying the oxide thickness. Thereafter, we have analyzed the effect of...A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported. The characteristics of both devices are observed as varying the oxide thickness. Thereafter, we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device. After simulation on the HSPICE tool, we observed that the high threshold voltage can be achieved at a low chiral vector pair. It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small. After that, we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices. We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect. It is observed that at below the 10 nm channel length, the threshold voltage is increased rapidly in the case of the CNTFET device, whereas in the case of the MOSFET device, the threshold voltage decreases drastically.展开更多
This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less s...This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties.Sensitivity analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart i.e.MOSFET,because various short channel effects are well controlled in this device.The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device.However,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.展开更多
We investigate the quantum-mechanical effects on the electrical properties of the double-gate j unction- less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the thre...We investigate the quantum-mechanical effects on the electrical properties of the double-gate j unction- less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.展开更多
基金Project Supported by Nature Science Foundation Project of CQ CSTC （2008BB615）.
文摘A new method of measuring the icing thickness of transmission lines on-line is proposed in this paper.In this method,the pictures of transmission lines which are photoed by the camera on the iron tower are processed immediately to extract the edges of the transmission line conductor and transmission line insulators.The icing thickness can be gained by comparing the edges of the iced transmission line and the uniced one.Two icing image edge extraction methods are described in detail,that is,a method based on the combination of the wavelet transform and the floating threshold method and a method based on the combination of the optimal threshold method and the mathematical morphology transform.The icing images from the artificial climatic chamber and transmission lines are used to test the methods above.The results show that the method based on the wavelet transform and the floating threshold method does well in the extraction of relatively smooth edges,such as glaze icing on conductor and icing on the insulator;meanwhile,the method based on the optimal threshold method and the mathematical morphology transform does well in the edge extraction of icing on the conductor,especially the opaque rime icing on the conductor with complicated edges.
文摘A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported. The characteristics of both devices are observed as varying the oxide thickness. Thereafter, we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device. After simulation on the HSPICE tool, we observed that the high threshold voltage can be achieved at a low chiral vector pair. It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small. After that, we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices. We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect. It is observed that at below the 10 nm channel length, the threshold voltage is increased rapidly in the case of the CNTFET device, whereas in the case of the MOSFET device, the threshold voltage decreases drastically.
文摘This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties.Sensitivity analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart i.e.MOSFET,because various short channel effects are well controlled in this device.The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device.However,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.
文摘We investigate the quantum-mechanical effects on the electrical properties of the double-gate j unction- less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.
