To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it i...To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.展开更多
Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% o...Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.展开更多
A new planar split dual gate （PSDG） MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculatio...A new planar split dual gate （PSDG） MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device characteristics, such as threshold voltage （Vt） and sub-threshold swing （SS）, as well as the device saturated current. The PSDG MOSFET transistor leakage current （loft） can be reduced as much as 78% of the traditional single gate MOSFET. The PSDG is fabricated and fully compatible with our conventional 0.18 μm logic process flow.展开更多
In August, 1997, a city-gate site was excavated by the Tang Luoyang City Archaeological Team, IA, CASS, in cooperation with capital construction. It lies in the west-east city wail between the Yuanbi and Yaoyi sub-cit...In August, 1997, a city-gate site was excavated by the Tang Luoyang City Archaeological Team, IA, CASS, in cooperation with capital construction. It lies in the west-east city wail between the Yuanbi and Yaoyi sub-cities in the northern part of the palace city of the Sui-Tang period Luoyang. The remains include city-gate platforms and their foundation-trenches. Besides, ruins of city wails were discovered stretching away from the western and eastern sides of the platforms.展开更多
文摘To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C.
文摘Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.
文摘A new planar split dual gate （PSDG） MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device characteristics, such as threshold voltage （Vt） and sub-threshold swing （SS）, as well as the device saturated current. The PSDG MOSFET transistor leakage current （loft） can be reduced as much as 78% of the traditional single gate MOSFET. The PSDG is fabricated and fully compatible with our conventional 0.18 μm logic process flow.
文摘In August, 1997, a city-gate site was excavated by the Tang Luoyang City Archaeological Team, IA, CASS, in cooperation with capital construction. It lies in the west-east city wail between the Yuanbi and Yaoyi sub-cities in the northern part of the palace city of the Sui-Tang period Luoyang. The remains include city-gate platforms and their foundation-trenches. Besides, ruins of city wails were discovered stretching away from the western and eastern sides of the platforms.
