Real-Time segmented pulse compression-detection is one of the key technologies of space-borne tracking receiver. Its implementation requires an optimized and dedicated hardware. The real-time processing places several...Real-Time segmented pulse compression-detection is one of the key technologies of space-borne tracking receiver. Its implementation requires an optimized and dedicated hardware. The real-time processing places several constraints such as area occupied, power comumption, and speed. A number of segmented compression techniques have been proposed to overcome these limitations and decrease the processing latency. However, relatively high power loss in the partial field could limit their implementation in many current real-time systems. A good theoretical model was designed with intersection signal accumulation to enhance signal- noise-ratio （SNR） gain of detecting signal in the paper. From the experimental results it is known that this approach works well for pulse compression-detection, which is better suited for implementation in the high performance of current field programmable gate array （FPGA） with dedicated hardware multipliers.展开更多
文摘Real-Time segmented pulse compression-detection is one of the key technologies of space-borne tracking receiver. Its implementation requires an optimized and dedicated hardware. The real-time processing places several constraints such as area occupied, power comumption, and speed. A number of segmented compression techniques have been proposed to overcome these limitations and decrease the processing latency. However, relatively high power loss in the partial field could limit their implementation in many current real-time systems. A good theoretical model was designed with intersection signal accumulation to enhance signal- noise-ratio （SNR） gain of detecting signal in the paper. From the experimental results it is known that this approach works well for pulse compression-detection, which is better suited for implementation in the high performance of current field programmable gate array （FPGA） with dedicated hardware multipliers.
