为降嵌入式以太网成本、提高效益,采用DSP(Digital Signal Processor)芯片和网卡接口控制芯片ENC28J60设计以太网控制器。研究了采用标准SPI(Serial Peripheral Interface)串行接口的新型独立以太网控制器ENC28J60的特点,以及与外部接...为降嵌入式以太网成本、提高效益,采用DSP(Digital Signal Processor)芯片和网卡接口控制芯片ENC28J60设计以太网控制器。研究了采用标准SPI(Serial Peripheral Interface)串行接口的新型独立以太网控制器ENC28J60的特点,以及与外部接口的硬件电路设计,分析了嵌入式TCP/IP协议的选取原则,DSP芯片对网卡接口控制芯片的控制过程和TCP/IP协议处理数据包的流程。该系统可以将数据按网络协议处理,实现数据的以太网传输。展开更多
With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced mi...With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.展开更多
文摘为降嵌入式以太网成本、提高效益,采用DSP(Digital Signal Processor)芯片和网卡接口控制芯片ENC28J60设计以太网控制器。研究了采用标准SPI(Serial Peripheral Interface)串行接口的新型独立以太网控制器ENC28J60的特点,以及与外部接口的硬件电路设计,分析了嵌入式TCP/IP协议的选取原则,DSP芯片对网卡接口控制芯片的控制过程和TCP/IP协议处理数据包的流程。该系统可以将数据按网络协议处理,实现数据的以太网传输。
文摘With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.
