Based on the Boltzmann transport equation of electrons and taking the scattering effect of electrons in the grain boundary as the boundary conditions of electrons transport in the grain, we presented a theoretical mod...Based on the Boltzmann transport equation of electrons and taking the scattering effect of electrons in the grain boundary as the boundary conditions of electrons transport in the grain, we presented a theoretical model for the Seebeck coefficient of bulk poly- crystalline thermoelectric materials, and applied it to studying the grain size effect on the Seebeck coefficient. Then we discussed the effects of transmissivity, temperature and the mean free path of electrons on the size effect. The results show that the proposed theoretical model is reasonable and effective and the predicted results for the Seebeck coefficient are in good agreement with the experimental data reported in literature. The bulk polycrystalline materials have notable (big) grain size effects on the Seebeck coefficient, and the influences of transmissivity, temperature and the mean free path of electrons on the Seebeck coefficient are also significant.展开更多
As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact...As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.展开更多
基金supported by the National Basic Research Program of China (Grant No. 2007CB607506)National Natural Science Foundation of China (Grant No. 10672070)Program for New Century Talent of the Ministry of Education (Grant No. NCET06-0896)
文摘Based on the Boltzmann transport equation of electrons and taking the scattering effect of electrons in the grain boundary as the boundary conditions of electrons transport in the grain, we presented a theoretical model for the Seebeck coefficient of bulk poly- crystalline thermoelectric materials, and applied it to studying the grain size effect on the Seebeck coefficient. Then we discussed the effects of transmissivity, temperature and the mean free path of electrons on the size effect. The results show that the proposed theoretical model is reasonable and effective and the predicted results for the Seebeck coefficient are in good agreement with the experimental data reported in literature. The bulk polycrystalline materials have notable (big) grain size effects on the Seebeck coefficient, and the influences of transmissivity, temperature and the mean free path of electrons on the Seebeck coefficient are also significant.
基金supported by the National Natural Science Foundation of China (Grant Nos.60725415 and 60971066)the National High-tech Program (Grant Nos.2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation (Grant No.ZHD200904)
文摘As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.
