提出了应用0.13μm CMOS工艺设计的具有高隔离度的Ka波段单刀双掷（Single Pole Double Throw,SPDT）开关。测试结果显示,在Ka波段此单片开关插损为2.7~3.7 d B,在35 GHz时测得的输入1dB压缩点（P_（-1dB））为8d Bm。通过使用并联NMOS...提出了应用0.13μm CMOS工艺设计的具有高隔离度的Ka波段单刀双掷（Single Pole Double Throw,SPDT）开关。测试结果显示,在Ka波段此单片开关插损为2.7~3.7 d B,在35 GHz时测得的输入1dB压缩点（P_（-1dB））为8d Bm。通过使用并联NMOS晶体管的拓扑结构并且使用高Q值的匹配网络,测得的开关在30~45 GHz有33~51 d B的隔离度。此Ka波段单刀双掷开关芯片的核心面积（die）仅仅为160×180μm2。展开更多
采用0.25μm Ga N HEMT工艺,研制了一款X波段发射前端多功能MMIC,片上集成了一个单刀双掷(SPDT)开关和一个功率放大器电路。其中SPDT开关采用对称的两路双器件并联结构,功率放大器采用三级放大拓扑结构设计,电路采用电抗匹配方式兼顾输...采用0.25μm Ga N HEMT工艺,研制了一款X波段发射前端多功能MMIC,片上集成了一个单刀双掷(SPDT)开关和一个功率放大器电路。其中SPDT开关采用对称的两路双器件并联结构,功率放大器采用三级放大拓扑结构设计,电路采用电抗匹配方式兼顾输出功率和效率。测试结果表明,在8~12 GHz频带内,芯片发射通道饱和输出功率为38.6~40.2 d Bm,功率附加效率为29%~34.5%,其中开关插入损耗约为0.8 d B,隔离度优于-45d B。该芯片面积为4 mm×2.1 mm。展开更多
This paper presents a 4×2 switching matrix implemented in the Win 0.5 μm Ga As pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of ...This paper presents a 4×2 switching matrix implemented in the Win 0.5 μm Ga As pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of 4 SPDT switch whose two output ports can simultaneously select the input port and a 4 to 8 bit digital decoder,both the radio frequency（RF） part and the digital part are integrated into one single chip. The chip is packaged in a low cost QFN24 plastic package. On chip shunt, capacitors at the input ports are taken to compensate for the bonding wire inductance effect. The designed switch matrix shows a good measured performance： the insertion loss is less than 5.5 dB, the isolation is no worse than 30 dB, the return loss of input ports and output ports is better than –10 dB, the input 1 dB compression point is better than 25.6 dBm, and the OIP3 is better than 37 dBm. The chip size of the switch matrix is only 1.45×1.45 mm^2.展开更多
在短波通信设备中,当预选器工作时,会有载波信号泄漏到后选器中;反之,当后选器工作时,也存在载波信号泄漏到预选器中。如果预/后选器隔离度低,这些泄漏的信号会和传输信号一同被放大,对通信设备性能造成不利影响。针对这一问题,提出了...在短波通信设备中,当预选器工作时,会有载波信号泄漏到后选器中;反之,当后选器工作时,也存在载波信号泄漏到预选器中。如果预/后选器隔离度低,这些泄漏的信号会和传输信号一同被放大,对通信设备性能造成不利影响。针对这一问题,提出了一种全方位提高短波预/后选器隔离度的设计方案。讨论了保护电路的设计以及PCB排版时应注意的接地问题。测试结果表明,预/后选器的隔离度达到60 d B以上,有效地解决了因载波泄漏导致通信设备性能不佳的问题。展开更多
文摘提出了应用0.13μm CMOS工艺设计的具有高隔离度的Ka波段单刀双掷（Single Pole Double Throw,SPDT）开关。测试结果显示,在Ka波段此单片开关插损为2.7~3.7 d B,在35 GHz时测得的输入1dB压缩点（P_（-1dB））为8d Bm。通过使用并联NMOS晶体管的拓扑结构并且使用高Q值的匹配网络,测得的开关在30~45 GHz有33~51 d B的隔离度。此Ka波段单刀双掷开关芯片的核心面积（die）仅仅为160×180μm2。
文摘采用0.25μm Ga N HEMT工艺,研制了一款X波段发射前端多功能MMIC,片上集成了一个单刀双掷(SPDT)开关和一个功率放大器电路。其中SPDT开关采用对称的两路双器件并联结构,功率放大器采用三级放大拓扑结构设计,电路采用电抗匹配方式兼顾输出功率和效率。测试结果表明,在8~12 GHz频带内,芯片发射通道饱和输出功率为38.6~40.2 d Bm,功率附加效率为29%~34.5%,其中开关插入损耗约为0.8 d B,隔离度优于-45d B。该芯片面积为4 mm×2.1 mm。
文摘This paper presents a 4×2 switching matrix implemented in the Win 0.5 μm Ga As pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of 4 SPDT switch whose two output ports can simultaneously select the input port and a 4 to 8 bit digital decoder,both the radio frequency（RF） part and the digital part are integrated into one single chip. The chip is packaged in a low cost QFN24 plastic package. On chip shunt, capacitors at the input ports are taken to compensate for the bonding wire inductance effect. The designed switch matrix shows a good measured performance： the insertion loss is less than 5.5 dB, the isolation is no worse than 30 dB, the return loss of input ports and output ports is better than –10 dB, the input 1 dB compression point is better than 25.6 dBm, and the OIP3 is better than 37 dBm. The chip size of the switch matrix is only 1.45×1.45 mm^2.
文摘在短波通信设备中,当预选器工作时,会有载波信号泄漏到后选器中;反之,当后选器工作时,也存在载波信号泄漏到预选器中。如果预/后选器隔离度低,这些泄漏的信号会和传输信号一同被放大,对通信设备性能造成不利影响。针对这一问题,提出了一种全方位提高短波预/后选器隔离度的设计方案。讨论了保护电路的设计以及PCB排版时应注意的接地问题。测试结果表明,预/后选器的隔离度达到60 d B以上,有效地解决了因载波泄漏导致通信设备性能不佳的问题。
