该文提出一种改进的低密度奇偶校验(Low Density Parity-Check,LDPC)码的加权比特翻转译码算法。该算法引入了变量节点的更新规则,对翻转函数的计算更加精确,同时能够有效弱化环路振荡引起的误码。仿真结果表明,与已有的基于幅度和的加...该文提出一种改进的低密度奇偶校验(Low Density Parity-Check,LDPC)码的加权比特翻转译码算法。该算法引入了变量节点的更新规则,对翻转函数的计算更加精确,同时能够有效弱化环路振荡引起的误码。仿真结果表明,与已有的基于幅度和的加权比特翻转译码算法(SMWBF)相比,在加性高斯白噪声信道下,该文算法在复杂度增加很小的情况下获得了误码率性能的有效提升。展开更多
An attenuated iterative reliability-based major- ity-logic （AIML） decoding algorithm for low-density parity-check （LDPC） codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based...An attenuated iterative reliability-based major- ity-logic （AIML） decoding algorithm for low-density parity-check （LDPC） codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based on the orthogonal check-sums of one-step majority- logic （OSMLG） decoding algorithm in conjunction with certain of reliability measures of the received symbols. Computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that, in binary-input additive white Gaussian noise （BI-AWGN） channel, the AIML decoding algorithm outperforms other popular iterative reliability-based major- ity-logic （IML） decoding algorithms with a slight increase in computational complexity. Within maximum iteration number of 5, the AIML algorithm can achieve almost identical error performance to sum-product algorithm （SPA）. No error floor effect can be observed for the AIML algorithm down to the bit error rate （BER） of 10- s, while error floor appears for SPA around the BER of 10 7 even with maximum iteration number of 100. Furthermore, the inherent feature of parallel procession for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping （WBF） algorithm.展开更多
The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low h...The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing（MOMP） algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing（OMP） technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-d B coding gain for Binary PhaseShift Keying（BPSK） in an Additive White Gaussian Noise（AWGN） channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.展开更多
文摘该文提出一种改进的低密度奇偶校验(Low Density Parity-Check,LDPC)码的加权比特翻转译码算法。该算法引入了变量节点的更新规则,对翻转函数的计算更加精确,同时能够有效弱化环路振荡引起的误码。仿真结果表明,与已有的基于幅度和的加权比特翻转译码算法(SMWBF)相比,在加性高斯白噪声信道下,该文算法在复杂度增加很小的情况下获得了误码率性能的有效提升。
文摘An attenuated iterative reliability-based major- ity-logic （AIML） decoding algorithm for low-density parity-check （LDPC） codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based on the orthogonal check-sums of one-step majority- logic （OSMLG） decoding algorithm in conjunction with certain of reliability measures of the received symbols. Computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that, in binary-input additive white Gaussian noise （BI-AWGN） channel, the AIML decoding algorithm outperforms other popular iterative reliability-based major- ity-logic （IML） decoding algorithms with a slight increase in computational complexity. Within maximum iteration number of 5, the AIML algorithm can achieve almost identical error performance to sum-product algorithm （SPA）. No error floor effect can be observed for the AIML algorithm down to the bit error rate （BER） of 10- s, while error floor appears for SPA around the BER of 10 7 even with maximum iteration number of 100. Furthermore, the inherent feature of parallel procession for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping （WBF） algorithm.
基金supported in part by the National Natural Science Foundation of China (Nos. 61101072 and 61132002)the new strategic industries development projects of Shenzhen city (No. ZDSY20120616141333842)Tsinghua University Initiative Scientific Research Program (No. 2012Z10132)
文摘The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing（MOMP） algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing（OMP） technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-d B coding gain for Binary PhaseShift Keying（BPSK） in an Additive White Gaussian Noise（AWGN） channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.
