A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is...A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.展开更多
A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output...A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.展开更多
文摘A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.
基金Project supported by the National Defense Pre-Research Project of China(No.51308010610)
文摘A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.
