This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error d...This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the C-element.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5%less energy and 33.1%less propagation delay than the triple modular redundancy（TMR）latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively.展开更多
Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventu...Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61404001,61306046)the Anhui Province University Natural Science Research Major Project(No.KJ2014ZD12)+1 种基金the Huainan Science and Technology Program(No.2013A4011)the National Natural Science Foundation of China(No.61371025)
文摘This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the C-element.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5%less energy and 33.1%less propagation delay than the triple modular redundancy（TMR）latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively.
基金supported by the National Natural Science Foundation of China (Nos. 60633060, 60876028).
文摘Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.
