The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is ...The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is observed for pMOSFETs with different channel lengths under hot-carrier stress.Thus,the relationships of oxide charge generation,including electron trapping and hole trapping effects,with different stress voltages and channel lengths are analyzed.It is also found that there is a two-step process in the generation of oxide charge for pMOSFETs.For a short stress time,electron trapping is predominant,whereas for a long stress time,hole trapping dominates the generation of oxide charge.展开更多
The mobility degradation induced by negative bias temperature instability(NBTI) is usually ignored in traditional NBTI modeling and simulation, resulting in overestimation of the circuit lifetime, especially after lon...The mobility degradation induced by negative bias temperature instability(NBTI) is usually ignored in traditional NBTI modeling and simulation, resulting in overestimation of the circuit lifetime, especially after longterm operation. In this paper, the mobility degradation is modeled in combination with the universal NBTI model.The coulomb scattering induced by interface states is revealed to be the dominant component responsible for mobility degradation. The proposed mobility degradation model fits the measured data well and provides an accurate solution for evaluating coupling of NBTI with HCI(hot carrier injection) and SHE(self-heating effect), which indicates that mobility degradation should be considered in long-term circuit aging simulation.展开更多
Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift...Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carder degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.展开更多
In this paper, we have studied hot carrier injection （HCI） different degradations are obtained from the experiment results. under alternant stress. Under different stress modes, The different alternate stresses can ...In this paper, we have studied hot carrier injection （HCI） different degradations are obtained from the experiment results. under alternant stress. Under different stress modes, The different alternate stresses can reduce or enhance the HC effect, which mainly depends on the latter condition of the stress cycle. In the stress mode A （DC stress with electron injection）, the degradation keeps increasing. In the stress modes B （DC stress and then stress with the smMlest gate injection） and C （DC stress and then stress with hole injection under Vg = 0 V and Vd = 1.8 V）, recovery appears in the second stress period. And in the stress mode D （DC stress and then stress with hole injection under Vg = -1.8 V and Vd = 1.8 V）, as the traps filled in by holes can be smaller or greater than the generated interface states, the continued degradation or recovery in different stress periods can be obtained.展开更多
In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Co...In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.展开更多
A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degr...A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.展开更多
文摘The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is observed for pMOSFETs with different channel lengths under hot-carrier stress.Thus,the relationships of oxide charge generation,including electron trapping and hole trapping effects,with different stress voltages and channel lengths are analyzed.It is also found that there is a two-step process in the generation of oxide charge for pMOSFETs.For a short stress time,electron trapping is predominant,whereas for a long stress time,hole trapping dominates the generation of oxide charge.
基金Project supported by the Shenzhen Science and Technology Project(Nos.ZDSYS201703031405137,JCYJ20170810163407761,(JCYJ20170818114156474)the PhD Start-up Fund of Natural Science Foundation of Guangdong Province(No.2015A030310499)the China Postdoctoral Science Foundation Funded Project(No.2015T80023)
文摘The mobility degradation induced by negative bias temperature instability(NBTI) is usually ignored in traditional NBTI modeling and simulation, resulting in overestimation of the circuit lifetime, especially after longterm operation. In this paper, the mobility degradation is modeled in combination with the universal NBTI model.The coulomb scattering induced by interface states is revealed to be the dominant component responsible for mobility degradation. The proposed mobility degradation model fits the measured data well and provides an accurate solution for evaluating coupling of NBTI with HCI(hot carrier injection) and SHE(self-heating effect), which indicates that mobility degradation should be considered in long-term circuit aging simulation.
基金supported by the National High Technology Research and Development Program of China (No. 2004AA1Z1060).
文摘Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carder degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.
基金supported by the National Key Science and Technology Special Project,China (Grant No. 2008ZX01002-002)the grant from the Major State Basic Research Development Program of China (973 Program,No. 2011CB309606)the Fundamental Research Funds for the Central Universities (Grant No. JY10000904009)
文摘In this paper, we have studied hot carrier injection （HCI） different degradations are obtained from the experiment results. under alternant stress. Under different stress modes, The different alternate stresses can reduce or enhance the HC effect, which mainly depends on the latter condition of the stress cycle. In the stress mode A （DC stress with electron injection）, the degradation keeps increasing. In the stress modes B （DC stress and then stress with the smMlest gate injection） and C （DC stress and then stress with hole injection under Vg = 0 V and Vd = 1.8 V）, recovery appears in the second stress period. And in the stress mode D （DC stress and then stress with hole injection under Vg = -1.8 V and Vd = 1.8 V）, as the traps filled in by holes can be smaller or greater than the generated interface states, the continued degradation or recovery in different stress periods can be obtained.
基金The Natural Science Foundation of Jiangsu Province(No.BK2008287)the Preresearch Project of the National Natural Science Foundation of Southeast University(No.XJ2008312)
文摘In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.
文摘A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.
