This paper describes a test architecture for minimum number of test configurations in test of FPGA （Field Programmable Gate Array） LUTs （Look Up Tables）. The test architecture includes a TPG （Test Pattern Genera...This paper describes a test architecture for minimum number of test configurations in test of FPGA （Field Programmable Gate Array） LUTs （Look Up Tables）. The test architecture includes a TPG （Test Pattern Generator） that is tested while it is generating test data for LEs （Logic Elements） that form the CUT （Circuit Under Test）. This scheme eliminates the need for switching LEs between CUT, TPG and ORA （Output Response Analyzer） and having to perform many more reconfiguratioas of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.展开更多
文摘This paper describes a test architecture for minimum number of test configurations in test of FPGA （Field Programmable Gate Array） LUTs （Look Up Tables）. The test architecture includes a TPG （Test Pattern Generator） that is tested while it is generating test data for LEs （Logic Elements） that form the CUT （Circuit Under Test）. This scheme eliminates the need for switching LEs between CUT, TPG and ORA （Output Response Analyzer） and having to perform many more reconfiguratioas of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.
