This paper describes a VLSI architecture used for implementation of fast Fourier transform, of which the computation cell(CC) implement the computation of 4-point DFT and multiplication of twiddle factors using radix-...This paper describes a VLSI architecture used for implementation of fast Fourier transform, of which the computation cell(CC) implement the computation of 4-point DFT and multiplication of twiddle factors using radix-4 pipeline computation method, and the address generator (AG) gives the addresses of both transform data and twiddle factors simultaneously. In addition, this paper also presents the recursive and cascade circuit configurations using the CC, AG and BFP overflow preventing scheme. Up to 64K-point FFT can be computed quickly and flexibly by using these two circuit configurations.展开更多
文摘This paper describes a VLSI architecture used for implementation of fast Fourier transform, of which the computation cell(CC) implement the computation of 4-point DFT and multiplication of twiddle factors using radix-4 pipeline computation method, and the address generator (AG) gives the addresses of both transform data and twiddle factors simultaneously. In addition, this paper also presents the recursive and cascade circuit configurations using the CC, AG and BFP overflow preventing scheme. Up to 64K-point FFT can be computed quickly and flexibly by using these two circuit configurations.
