通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试...通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试方法进行测试,同时设计一些控制模块优化测试结构;经验证,应用这些策略,在满足了功耗和面积要求的前提下,系统总测试覆盖率达到了98.69%,且具有期望的可控制性和可观察性;因此在SOC设计中应灵活采用不同测试策略,合理分配测试资源从而达到预期的测试效果。展开更多
The paper proposes a novel ATPG (Automatic Test Pattern Generation) methodbased on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware DescriptionLanguage). The method is simulation-based. Firstly, ...The paper proposes a novel ATPG (Automatic Test Pattern Generation) methodbased on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware DescriptionLanguage). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptionsto Process Controlling Trees (PCT) and Data Dependency Graphs (DDG), which are used forbehavioral simulation and data tracing. Transfer faults are extracted from DDG edges, whichcompose a fault set needed for test generation. Then, simulation begins without specifying inputsin advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally,when the simulation ends, the partially fixed input sequence is the generated test sequence. Theproposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to coveruncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests withgood quality. Experimental results demonstrate that the proposed method is better than ARTISTin three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length isshorter by 52%; and (3) the fault coverage is higher by 0.89%.展开更多
The subunit Ⅱ of chloroplast ATP synthase is one of the two peripheral stalks, which associates the catalytic CF1 with mem-brane-spanning CFo . Although the structural and functional roles of chloroplast ATP synthase...The subunit Ⅱ of chloroplast ATP synthase is one of the two peripheral stalks, which associates the catalytic CF1 with mem-brane-spanning CFo . Although the structural and functional roles of chloroplast ATP synthase have been extensively examined, the physiological significance of subunit Ⅱ in vivo is still unclear. In this work, we identified one Arabidopsis T-DNA insertion mutant of atpG gene encoding the subunit Ⅱ of chloroplast ATP synthase. The atpg null mutant displayed an albino lethal pheno-type, as it could not grow photoautotrophically. Transmission electron microscopy analysis showed that chloroplasts of atpg lacked the organized thylakoid membranes. Loss of subunit Ⅱ affected the accumulation of CF1-CFo complex, however, it did not seem to have an effect on the CF1 assembly. The light induced ATP formation of atpg was significantly reduced compared with the wild type. Based on these results, we suggested that ATPG was essential for the accumulation and function of chloroplast ATP synthase.展开更多
ATPG(automatic test pattern generation)是VLSI(very large scale integration circuits)电路测试中非常重要的技术,它的好坏直接影响测试成本与开销.然而现有的并行ATPG方法普遍存在负载不均衡、并行策略单一、存储开销大和数据局部...ATPG(automatic test pattern generation)是VLSI(very large scale integration circuits)电路测试中非常重要的技术,它的好坏直接影响测试成本与开销.然而现有的并行ATPG方法普遍存在负载不均衡、并行策略单一、存储开销大和数据局部性差等问题.由于图计算的高并行度和高扩展性等优点,快速、高效、低存储开销和高可扩展性的图计算系统可能是有效支持ATPG的重要工具,这将对减少测试成本显得尤为重要.本文将对图计算在组合ATPG中的应用进行探究;介绍图计算模型将ATPG算法转化为图算法的方法;分析现有图计算系统应用于ATPG面临的挑战;提出面向ATPG的单机图计算系统,并从基于传统架构的优化、新兴硬件的加速和基于新兴存储器件的优化几个方面,对图计算系统支持ATPG所面临的挑战和未来研究方向进行了讨论.展开更多
Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic t...Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.展开更多
文摘通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试方法进行测试,同时设计一些控制模块优化测试结构;经验证,应用这些策略,在满足了功耗和面积要求的前提下,系统总测试覆盖率达到了98.69%,且具有期望的可控制性和可观察性;因此在SOC设计中应灵活采用不同测试策略,合理分配测试资源从而达到预期的测试效果。
文摘The paper proposes a novel ATPG (Automatic Test Pattern Generation) methodbased on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware DescriptionLanguage). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptionsto Process Controlling Trees (PCT) and Data Dependency Graphs (DDG), which are used forbehavioral simulation and data tracing. Transfer faults are extracted from DDG edges, whichcompose a fault set needed for test generation. Then, simulation begins without specifying inputsin advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally,when the simulation ends, the partially fixed input sequence is the generated test sequence. Theproposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to coveruncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests withgood quality. Experimental results demonstrate that the proposed method is better than ARTISTin three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length isshorter by 52%; and (3) the fault coverage is higher by 0.89%.
基金supported by the National Natural Science Foundation of China (31070215 and 31100181)the State Key Basic Research and Development Program of China (2009CB118504)
文摘The subunit Ⅱ of chloroplast ATP synthase is one of the two peripheral stalks, which associates the catalytic CF1 with mem-brane-spanning CFo . Although the structural and functional roles of chloroplast ATP synthase have been extensively examined, the physiological significance of subunit Ⅱ in vivo is still unclear. In this work, we identified one Arabidopsis T-DNA insertion mutant of atpG gene encoding the subunit Ⅱ of chloroplast ATP synthase. The atpg null mutant displayed an albino lethal pheno-type, as it could not grow photoautotrophically. Transmission electron microscopy analysis showed that chloroplasts of atpg lacked the organized thylakoid membranes. Loss of subunit Ⅱ affected the accumulation of CF1-CFo complex, however, it did not seem to have an effect on the CF1 assembly. The light induced ATP formation of atpg was significantly reduced compared with the wild type. Based on these results, we suggested that ATPG was essential for the accumulation and function of chloroplast ATP synthase.
文摘ATPG(automatic test pattern generation)是VLSI(very large scale integration circuits)电路测试中非常重要的技术,它的好坏直接影响测试成本与开销.然而现有的并行ATPG方法普遍存在负载不均衡、并行策略单一、存储开销大和数据局部性差等问题.由于图计算的高并行度和高扩展性等优点,快速、高效、低存储开销和高可扩展性的图计算系统可能是有效支持ATPG的重要工具,这将对减少测试成本显得尤为重要.本文将对图计算在组合ATPG中的应用进行探究;介绍图计算模型将ATPG算法转化为图算法的方法;分析现有图计算系统应用于ATPG面临的挑战;提出面向ATPG的单机图计算系统,并从基于传统架构的优化、新兴硬件的加速和基于新兴存储器件的优化几个方面,对图计算系统支持ATPG所面临的挑战和未来研究方向进行了讨论.
文摘Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.
