We investigate the transient behavior of an n-type double gate negative capacitance junctionless tun- nel field effect transistor （NC-JLTFET）. The structure is realized by using the work-function engineering of meta...We investigate the transient behavior of an n-type double gate negative capacitance junctionless tun- nel field effect transistor （NC-JLTFET）. The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n＋ silicon channel and a ferroelectric gate stack to get negative capacitance be- havior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.展开更多
We propose a unique approach for realizing dopingless impact ionization MOS （DL-IMOS） based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form ...We propose a unique approach for realizing dopingless impact ionization MOS （DL-IMOS） based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.展开更多
文摘We investigate the transient behavior of an n-type double gate negative capacitance junctionless tun- nel field effect transistor （NC-JLTFET）. The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n＋ silicon channel and a ferroelectric gate stack to get negative capacitance be- havior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.
文摘We propose a unique approach for realizing dopingless impact ionization MOS （DL-IMOS） based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.
