Triple-level cell(TLC)NAND flash is increasingly adopted to build solid-state drives(SSDs)for modern computer systems.While TLC NAND flash effectively improves storage density,it faces severe reliability issues;in par...Triple-level cell(TLC)NAND flash is increasingly adopted to build solid-state drives(SSDs)for modern computer systems.While TLC NAND flash effectively improves storage density,it faces severe reliability issues;in partic-ular,the pages exhibit different raw bit error rates(RBERs).Integrating strong low-density parity-check(LDPC)code helps to improve reliability but suffers from prolonged and proportional read latency due to multiple read retries for worse pages.The straightforward idea is that dispersing page-size data across several pages in different types can achieve a low-er average RBER and reduce the read latency.However,directly implementing this simple idea into flash translation lay-er(FTL)induces the read amplification issue as one logic page residing in more than one physical page brings several read operations.In this paper,we propose the Dynamic Request Interleaving(DIR)technology for improving the performance of TLC NAND flash-based SSDs,in particular,the aged ones with large RBERs.DIR exploits the observation that the la-tency of an I/O request is determined,without considering the queuing time,by the access of the slowest device page,i.e.,the page that has the highest RBER.By grouping consecutive logical pages that have high locality and interleaving their encoded data in different types of device pages that have different RBERs,DIR effectively reduces the number of read re-tries for LDPC with limited read amplification.To meet the requirement of allocating hybrid page types for interleaved data,we also design a page-interleaving friendly page allocation scheme,which splits all the planes into multi-plane re-gions for storing the interleaved data and single-plane regions for storing the normal data.The pages in the multi-plane re-gion can be read/written in parallel by the proposed multi-plane command and avoid the read amplification issue.Based on the DIR scheme and the proposed page allocation scheme,we build DIR-enable FTL,which integrates the proposed schemes into the FTL with some modificatio展开更多
基金This work was supported by the National Key Research and Development Project of China under Grant No.2017YFB1001701the National Natural Science Foundation of China under Grant No.61972311in part by Shandong Provincial Natural Science Foundation of China under Grant No.ZR2019LZH007.
文摘Triple-level cell(TLC)NAND flash is increasingly adopted to build solid-state drives(SSDs)for modern computer systems.While TLC NAND flash effectively improves storage density,it faces severe reliability issues;in partic-ular,the pages exhibit different raw bit error rates(RBERs).Integrating strong low-density parity-check(LDPC)code helps to improve reliability but suffers from prolonged and proportional read latency due to multiple read retries for worse pages.The straightforward idea is that dispersing page-size data across several pages in different types can achieve a low-er average RBER and reduce the read latency.However,directly implementing this simple idea into flash translation lay-er(FTL)induces the read amplification issue as one logic page residing in more than one physical page brings several read operations.In this paper,we propose the Dynamic Request Interleaving(DIR)technology for improving the performance of TLC NAND flash-based SSDs,in particular,the aged ones with large RBERs.DIR exploits the observation that the la-tency of an I/O request is determined,without considering the queuing time,by the access of the slowest device page,i.e.,the page that has the highest RBER.By grouping consecutive logical pages that have high locality and interleaving their encoded data in different types of device pages that have different RBERs,DIR effectively reduces the number of read re-tries for LDPC with limited read amplification.To meet the requirement of allocating hybrid page types for interleaved data,we also design a page-interleaving friendly page allocation scheme,which splits all the planes into multi-plane re-gions for storing the interleaved data and single-plane regions for storing the normal data.The pages in the multi-plane re-gion can be read/written in parallel by the proposed multi-plane command and avoid the read amplification issue.Based on the DIR scheme and the proposed page allocation scheme,we build DIR-enable FTL,which integrates the proposed schemes into the FTL with some modificatio
