This work presents a flexible/unified hardware architecture of Elliptic-curve Cryptography(ECC)and PRESENT for cryptographic applications.The features of the proposed work are(i)computation of only the point multiplic...This work presents a flexible/unified hardware architecture of Elliptic-curve Cryptography(ECC)and PRESENT for cryptographic applications.The features of the proposed work are(i)computation of only the point multiplication operation of ECC over GF(2163)for a 163-bit key generation,(ii)execution of only the variant of an 80-bit PRESENT block cipher for data encryption&decryption and(iii)execution of point multiplication operation(ECC algorithm)along with the data encryption and decryption(PRESENT algorithm).To establish an area overhead for the flexible design,dedicated hardware architectures of ECC and PRESENT are implemented in the first step,and a sum of their hardware area is computed.Then,the implementation of the proposed flexible architecture for ECC and PRESENT algorithms is presented.Implementation results regarding the area,clock cycles,latency,clock frequency,and power after the place-and-route level on Xilinx Virtex-5,Virtex-6,and Virtex-7 FPGA devices are presented.Hence,the implementation results and comparisons show that the proposed architecture suits applications demanding flexible implementation of cryptographic applications.展开更多
基金The authors would like to thank the Deanship of Scientific Research at Umm Al-Qura University for supporting this work by Grant Code:(22UQU4320020DSR01).
文摘This work presents a flexible/unified hardware architecture of Elliptic-curve Cryptography(ECC)and PRESENT for cryptographic applications.The features of the proposed work are(i)computation of only the point multiplication operation of ECC over GF(2163)for a 163-bit key generation,(ii)execution of only the variant of an 80-bit PRESENT block cipher for data encryption&decryption and(iii)execution of point multiplication operation(ECC algorithm)along with the data encryption and decryption(PRESENT algorithm).To establish an area overhead for the flexible design,dedicated hardware architectures of ECC and PRESENT are implemented in the first step,and a sum of their hardware area is computed.Then,the implementation of the proposed flexible architecture for ECC and PRESENT algorithms is presented.Implementation results regarding the area,clock cycles,latency,clock frequency,and power after the place-and-route level on Xilinx Virtex-5,Virtex-6,and Virtex-7 FPGA devices are presented.Hence,the implementation results and comparisons show that the proposed architecture suits applications demanding flexible implementation of cryptographic applications.
