After a prolonged debate and discussion,the World Health Organization(WHO)relisted'snakebite'under Category'A'of'Neglected Tropical Diseases'(NTDs)in June 2017 hoping to diminish its burden on ...After a prolonged debate and discussion,the World Health Organization(WHO)relisted'snakebite'under Category'A'of'Neglected Tropical Diseases'(NTDs)in June 2017 hoping to diminish its burden on people.Earlier,in March 2009,WHO added snakebite to its official list of NTDs but later downgraded to'Other Neglected Conditions',a list reduced in importance[1,2].Obviously,the recent inclusion of snakebite in NTDs was due to the estimation of huge toll of deaths due to snake envenomation in tropical countries as supported by the multiple reports.This inclusion will expedite the process of developing better management protocols and infusing funds for such affected countries.展开更多
This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDL...This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDLTEFT gives the superior results with high ON state current （/ON - 0.56 mA/um）, ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing （AV-SS -- 48 mV/dec）. The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.展开更多
In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. I...In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. It is compared with conventional doping-less TFET（DLTFET） and dual material gate doping-less TFET（DMG_DLTFET） on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current（I_（ON） =94 μA/ μm）, I_（ON）/I_（OFF）（≈1.36×10^（13））, point（≈3 mV/dec） and average subthreshold slope（AV-SSD40.40 mV/dec）. The proposed device offers low total gate capacitance（C_（gg）/ along with higher drive current. However, with a better transconductance（g_m） and cut-off frequency（f_T）, the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage（V_（EA）/ and output conductance（gd/ are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices.From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.展开更多
In this paper,we address the issue of peak-to-average power ratio(PAPR)reduction in large-scale multiuser multiple-input multiple-output(MU-MIMO)orthogonal frequency-division multiplexing(OFDM)systems.PAPR reduction a...In this paper,we address the issue of peak-to-average power ratio(PAPR)reduction in large-scale multiuser multiple-input multiple-output(MU-MIMO)orthogonal frequency-division multiplexing(OFDM)systems.PAPR reduction and the multiuser interference(MUI)cancellation problem are jointly formulated as an l_(∞)-norm based composite convex optimization problem,which can be solved efficiently using the iterative proximal gradient method.The proximal operator associated with l_(∞)-norm is evaluated using a low-cost sorting algorithm.The proposed method adaptively chooses the step size to accelerate convergence.Simulation results reveal that the proximal gradient method converges swiftly while provid-ing considerable PAPR reduction and lower out-of-band radiation.展开更多
A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of...A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.展开更多
The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain ...The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are： transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits （FOMs） are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate （L 1） for a given gate length （L） are also studied and the optimum lengths La under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.展开更多
文摘After a prolonged debate and discussion,the World Health Organization(WHO)relisted'snakebite'under Category'A'of'Neglected Tropical Diseases'(NTDs)in June 2017 hoping to diminish its burden on people.Earlier,in March 2009,WHO added snakebite to its official list of NTDs but later downgraded to'Other Neglected Conditions',a list reduced in importance[1,2].Obviously,the recent inclusion of snakebite in NTDs was due to the estimation of huge toll of deaths due to snake envenomation in tropical countries as supported by the multiple reports.This inclusion will expedite the process of developing better management protocols and infusing funds for such affected countries.
文摘This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDLTEFT gives the superior results with high ON state current （/ON - 0.56 mA/um）, ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing （AV-SS -- 48 mV/dec）. The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.
文摘In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. It is compared with conventional doping-less TFET（DLTFET） and dual material gate doping-less TFET（DMG_DLTFET） on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current（I_（ON） =94 μA/ μm）, I_（ON）/I_（OFF）（≈1.36×10^（13））, point（≈3 mV/dec） and average subthreshold slope（AV-SSD40.40 mV/dec）. The proposed device offers low total gate capacitance（C_（gg）/ along with higher drive current. However, with a better transconductance（g_m） and cut-off frequency（f_T）, the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage（V_（EA）/ and output conductance（gd/ are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices.From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.
文摘In this paper,we address the issue of peak-to-average power ratio(PAPR)reduction in large-scale multiuser multiple-input multiple-output(MU-MIMO)orthogonal frequency-division multiplexing(OFDM)systems.PAPR reduction and the multiuser interference(MUI)cancellation problem are jointly formulated as an l_(∞)-norm based composite convex optimization problem,which can be solved efficiently using the iterative proximal gradient method.The proximal operator associated with l_(∞)-norm is evaluated using a low-cost sorting algorithm.The proposed method adaptively chooses the step size to accelerate convergence.Simulation results reveal that the proximal gradient method converges swiftly while provid-ing considerable PAPR reduction and lower out-of-band radiation.
文摘A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.
文摘The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are： transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits （FOMs） are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate （L 1） for a given gate length （L） are also studied and the optimum lengths La under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.
