For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel fi...For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.展开更多
We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelli...We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.展开更多
We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET i...We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.展开更多
This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to imp...This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.展开更多
This paper presents a floating resistor employing CIDITA (current inverting differential input transconductance amplifier). The proposed floating resistor is based on CMOS technology of 0.18 μm. For the realization o...This paper presents a floating resistor employing CIDITA (current inverting differential input transconductance amplifier). The proposed floating resistor is based on CMOS technology of 0.18 μm. For the realization of this floating inductor, two CIDITA have been cascaded together, no other passive elements are used, giving advantage of reduced chip area and hence reduced losses. The given circuit topology has an advantage of realizing both positive and negative resistors. This paper presents a simple circuitry of floating resistor in which the value of resistance can be tuned by adjusting the gate voltage of MOSFET. The PSpice simulation result shows constant resistance of 1.6 K<span style="white-space:nowrap;">Ω for frequency bandwidth of 1 Hz to 1 MHz, with supply voltage of ±1.25 volts.展开更多
文摘For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.
文摘We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.
文摘We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.
文摘This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.
文摘This paper presents a floating resistor employing CIDITA (current inverting differential input transconductance amplifier). The proposed floating resistor is based on CMOS technology of 0.18 μm. For the realization of this floating inductor, two CIDITA have been cascaded together, no other passive elements are used, giving advantage of reduced chip area and hence reduced losses. The given circuit topology has an advantage of realizing both positive and negative resistors. This paper presents a simple circuitry of floating resistor in which the value of resistance can be tuned by adjusting the gate voltage of MOSFET. The PSpice simulation result shows constant resistance of 1.6 K<span style="white-space:nowrap;">Ω for frequency bandwidth of 1 Hz to 1 MHz, with supply voltage of ±1.25 volts.
