In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems a...In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW.展开更多
In this paper, an ultra-low power adder cell is proposed. With cascading two XNOR cells, the sum of two inputs is achieved. Regarding to advantages of m-GDI XNOR cell, we constructed the adder cell based on this archi...In this paper, an ultra-low power adder cell is proposed. With cascading two XNOR cells, the sum of two inputs is achieved. Regarding to advantages of m-GDI XNOR cell, we constructed the adder cell based on this architecture. The simulation results show that the power consumption of the adder cell designed with GDI technology is 12.993 μw, whereas for this cell designed with m-GDI technology is 4.1628 μw, which both are designed at 0.18 um technology. Moreover, simulation results in 90 nm CMOS technology for m-GDI adder cell show average power consumption of 0.90262 μw and 6.3222 μw in 200 MHz and 2GHz, respectively.展开更多
文摘In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW.
文摘In this paper, an ultra-low power adder cell is proposed. With cascading two XNOR cells, the sum of two inputs is achieved. Regarding to advantages of m-GDI XNOR cell, we constructed the adder cell based on this architecture. The simulation results show that the power consumption of the adder cell designed with GDI technology is 12.993 μw, whereas for this cell designed with m-GDI technology is 4.1628 μw, which both are designed at 0.18 um technology. Moreover, simulation results in 90 nm CMOS technology for m-GDI adder cell show average power consumption of 0.90262 μw and 6.3222 μw in 200 MHz and 2GHz, respectively.
