An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Fiv...An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.展开更多
A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-...A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.展开更多
This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By m...This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.展开更多
A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I...A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor＇s 0.18-μm RF CMOS with an area of 6.1 mm^2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/＋9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_（1dB） better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.展开更多
基金supported by the National Eleven-Five Project Funding (No.51308020403)the Science and Technology Commission ofShanghai Municipality (No.08706200700)
文摘An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.
基金supported by the National Eleven-Five Project Funding(No.51308020403)the Science and Technology Commission of Shanghai Municipality(No.08706200700)the National High Technology Research and Development Program of China(No.2009AA01Z261)
文摘A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.
基金supported by the National Program of the 11th 5-Year-Plan(No.51308020403)the IC Design Program of the Shanghai Science Committee(No.08706200700)
文摘This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.
基金Project supported by the National Hi-Tech R&D Program of China(No.2009AA01Z261)the National Defense R&D Program of China (No.51308020403)the Shanghai IC Design Special Project,China(No.08706200700).
文摘A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor＇s 0.18-μm RF CMOS with an area of 6.1 mm^2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/＋9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_（1dB） better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.
