An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critic...An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the re- timed circuit with the near-optimal clock period. Compared with Singh＇s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table （LUT） count by 5% while improv- ing the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.展开更多
基金Supported by Major National Scientific Research Plan (No. 2011CB933202)
文摘An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the re- timed circuit with the near-optimal clock period. Compared with Singh＇s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table （LUT） count by 5% while improv- ing the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.
