This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth...This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.展开更多
A frequency-domain equalizer with a mixed-signal adaptive control loop and a novel baseline wander （BLW） canceller are proposed. The equalizer is independent of channel-modeling accuracy,and its control loop is intr...A frequency-domain equalizer with a mixed-signal adaptive control loop and a novel baseline wander （BLW） canceller are proposed. The equalizer is independent of channel-modeling accuracy,and its control loop is intrinsically stable. An AGC function is incorporated into the equalizer without an extra AGC circuit. The proposed BLW canceller uses a peak detector to monitor the BLW and full feedback method to accomplish BLW canceling. High canceling accuracy and robust performance are achieved. The circuits are tested in 0.25μm CMOS technology. Better performance and smaller silicon area are achieved compared with results in the literature.展开更多
文摘This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.
文摘A frequency-domain equalizer with a mixed-signal adaptive control loop and a novel baseline wander （BLW） canceller are proposed. The equalizer is independent of channel-modeling accuracy,and its control loop is intrinsically stable. An AGC function is incorporated into the equalizer without an extra AGC circuit. The proposed BLW canceller uses a peak detector to monitor the BLW and full feedback method to accomplish BLW canceling. High canceling accuracy and robust performance are achieved. The circuits are tested in 0.25μm CMOS technology. Better performance and smaller silicon area are achieved compared with results in the literature.
