A novel double-n equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in th...A novel double-n equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in the global model and the model equations in the local model. The major parasitic effects, including the skin effect, the proximity effect, the inductive and capacitive loss in the substrate, and the distributed effect, are analytically calculated with geometric and process parameters in the locaMevel. As accurate values of the layout and process parameters are difficult to obtain, a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level. Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions. A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-μm SiGe BiCMOS process with 100 Ω/cm substrate resistivity to verify the proposed model. Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.展开更多
A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 （MM20） is presented. The weak avalanche effect and the power dissipation caused by self-heating are described. The RF paras...A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 （MM20） is presented. The weak avalanche effect and the power dissipation caused by self-heating are described. The RF parasitic elements are extracted directly from measured S-parameters with analytical methods. Their final values can be obtained quickly and accurately through the necessary optimization. The model is validated in DC,AC small-signal,and large-signal analyses for an RF-SOI LDMOS of 20-fingers （channel mask length, L = 1μm,finger width, W = 50μm） gate with high resistivity substrate and body-contact. Excellent agreement is achieved between simulated and measured results for DC, S- parameters （10MHz-0.01GHz）, and power characteristics, which shows our model is accurate and reliable. MM20 is improved for RF-SOI LDMOS large-signal applications. This model has been implemented in Verilog-A using the ADS circuit simulator （hpeesofsim）.展开更多
基金Project supported by the State Key Development Program for Basic Research of China(No.2010CB327403)
文摘A novel double-n equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in the global model and the model equations in the local model. The major parasitic effects, including the skin effect, the proximity effect, the inductive and capacitive loss in the substrate, and the distributed effect, are analytically calculated with geometric and process parameters in the locaMevel. As accurate values of the layout and process parameters are difficult to obtain, a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level. Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions. A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-μm SiGe BiCMOS process with 100 Ω/cm substrate resistivity to verify the proposed model. Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.
文摘A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 （MM20） is presented. The weak avalanche effect and the power dissipation caused by self-heating are described. The RF parasitic elements are extracted directly from measured S-parameters with analytical methods. Their final values can be obtained quickly and accurately through the necessary optimization. The model is validated in DC,AC small-signal,and large-signal analyses for an RF-SOI LDMOS of 20-fingers （channel mask length, L = 1μm,finger width, W = 50μm） gate with high resistivity substrate and body-contact. Excellent agreement is achieved between simulated and measured results for DC, S- parameters （10MHz-0.01GHz）, and power characteristics, which shows our model is accurate and reliable. MM20 is improved for RF-SOI LDMOS large-signal applications. This model has been implemented in Verilog-A using the ADS circuit simulator （hpeesofsim）.
