In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient sig...In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.展开更多
Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/c...Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.展开更多
Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap ch...Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.展开更多
The effects of total ionizing dose radiation on direct current （DC） and small-signal radio frequency （RF） performance of multi-finger RF partial deplete silicon-on-insulator lateral double diffused MOS （PDSOI LD...The effects of total ionizing dose radiation on direct current （DC） and small-signal radio frequency （RF） performance of multi-finger RF partial deplete silicon-on-insulator lateral double diffused MOS （PDSOI LDMOS） transistors are investigated. The radiation response of the LDMOS transistors with different device structures is characterized for an equivalent gamma dose up to 1Mrad（Si） at room temperature. The front and back gate threshold voltages, off-state leak- age, transconductance, and output characteristics are measured before and after radiation, and the results show a significant degradation of DC performance. Moreover, high frequency measurements for the irradiated transistors indicate remarkable declines of S-parameters, cutoff frequency, and maximum oscillation frequency to 1Mrad（Si） exposure levels. Compared to the transistors with the BTS contact structure,the transistors with the LBBC contact do not show its excellent DC radiation hardness when the transistors operate at alternating current （AC） mode.展开更多
ISFET(Ion Sensitive Field Effect Transistors)是1种可与CMOS工艺兼容的离子敏感场效应晶体管.随着传感器阵列集成度的不断增加,鉴于响应速度、功耗和成本的局限性,单个ISFET的检测电路不适于大规模集成化的检测系统.从集成化的角度出...ISFET(Ion Sensitive Field Effect Transistors)是1种可与CMOS工艺兼容的离子敏感场效应晶体管.随着传感器阵列集成度的不断增加,鉴于响应速度、功耗和成本的局限性,单个ISFET的检测电路不适于大规模集成化的检测系统.从集成化的角度出发,在分析多个读出电路的基础上,比较各自的性能特点,得出1种脉冲宽度调节读出电路,在功耗、转换速度和结构方面都有优势,适合于大规模ISFET传感器阵列的数据读取.并应用分立元件对电路性能进行了验证,通过FPGA采集读出电路输出数据,验证其具有良好的稳定性和可行性.展开更多
文摘In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.
基金Project supported by the National Natural Science Foundation of China(Grant No.616340084)the Youth Innovation Promotion Association of CAS(Grant No.2014101)+1 种基金the International Cooperation Project of CASthe Austrian-Chinese Cooperative R&D Projects(Grant No.172511KYSB20150006)
文摘Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.
基金the National Natural Science Foundation of China(Grant Nos.12105340,12035019,and12075290)the Youth Innovation Promotion Association of the Chinese Academy of Sciences(Grant No.2020412)。
文摘Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.
基金National Nature Science Foundation of China(No.60576051)~~
文摘The effects of total ionizing dose radiation on direct current （DC） and small-signal radio frequency （RF） performance of multi-finger RF partial deplete silicon-on-insulator lateral double diffused MOS （PDSOI LDMOS） transistors are investigated. The radiation response of the LDMOS transistors with different device structures is characterized for an equivalent gamma dose up to 1Mrad（Si） at room temperature. The front and back gate threshold voltages, off-state leak- age, transconductance, and output characteristics are measured before and after radiation, and the results show a significant degradation of DC performance. Moreover, high frequency measurements for the irradiated transistors indicate remarkable declines of S-parameters, cutoff frequency, and maximum oscillation frequency to 1Mrad（Si） exposure levels. Compared to the transistors with the BTS contact structure,the transistors with the LBBC contact do not show its excellent DC radiation hardness when the transistors operate at alternating current （AC） mode.
文摘ISFET(Ion Sensitive Field Effect Transistors)是1种可与CMOS工艺兼容的离子敏感场效应晶体管.随着传感器阵列集成度的不断增加,鉴于响应速度、功耗和成本的局限性,单个ISFET的检测电路不适于大规模集成化的检测系统.从集成化的角度出发,在分析多个读出电路的基础上,比较各自的性能特点,得出1种脉冲宽度调节读出电路,在功耗、转换速度和结构方面都有优势,适合于大规模ISFET传感器阵列的数据读取.并应用分立元件对电路性能进行了验证,通过FPGA采集读出电路输出数据,验证其具有良好的稳定性和可行性.
