随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输...随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 m V到电源电压减去50 m V,实现了输入输出轨到轨的目标。展开更多
A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structu...A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.展开更多
文摘随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 m V到电源电压减去50 m V,实现了输入输出轨到轨的目标。
基金The National High Technology Research and Devel-opment Program of China (863Program) (No.2001AA312010).
文摘A 10 Gbit/s 1：4 demultiplexer（DEMUX） fabricated in 0. 18 μm CMOS （complementary metal-oxidesemiconductor transistor） technology for optical-fiber-link is presented. The system is constructed in tree-type structure and it includes a high-speed 1 ： 2 DEMUX, two low-speed 1 ： 2 DEMUXs, a divider, and input and output buffers for data and dock. To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1 ： 2 DEMUX and the 5 GHz 1 ： 2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed l ： 2 DEMUXs. Measured results at 10 Gbit/s by 23^31 -1 pseudo random bit sequences （PRBS） via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage. The die area of the DEMUX is 0. 65 mm × 0. 75 mm.
